Method of erasing a flash memory cell

Details Method of erasing a flash memory cell Method of erasing a flash memory cell

2006-07-04

2006-07-04

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185270, C365S185330

Reexamination Certificate

active

07072226

ABSTRACT:
Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.

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Korean Intellectual Property Office Official Action dated May 27, 2003 (2 pages).

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