Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-01-24
2003-11-04
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300
Reexamination Certificate
active
06643184
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of semiconductor memory devices, and, more particularly, to non-volatile, electrically erasable memories such as flash memories.
BACKGROUND OF THE INVENTION
A flash memory is a particular type of E
2
PROM (Electrical Erasable Programmable Read-Only Memory) that is erased in blocks instead of one byte at a time (typically in-system, without requiring any special power supply voltage). This results in a very simple structure of the flash memory, which can be manufactured at low cost and with high density. As a consequence, the flash memory is well suited to a number of end-product applications, such as PCs (Personal Computers), cellular phones, automotive devices, digital still cameras, and the like.
The flash memory is integrated in a chip of semiconductor material and includes one or more sectors, each one formed in a respective insulated well (body). The sector comprises a matrix of memory cells with a plurality of rows and columns; the memory cells of each row are connected to a respective word line, while the memory cells of each column are connected to a respective bit line. Typically, each memory cell consists of a MOS transistor with a floating gate (insulated by means of a thin oxide layer).
A not-programmed transistor has a low threshold voltage; therefore, when the transistor is selected, a current flows through the respective bit line (corresponding to a logic value 1). The transistor is programmed by injecting an electric charge into its floating gate. In this condition, the transistor has a high threshold voltage; therefore, when the transistor is selected, no current flows through the respective bit line (corresponding to a logic value 0).
The flash memory is erased by selecting and discharging all the transistors of a sector at the same time. Particularly, the transistors are at first pre-programmed to the logic value 0; in this way, all the transistors undergo the same programming and erasing cycles during the life of the flash memory, so that a uniform degradation of the transistors with time is ensured. The transistors are then erased by applying a series of erasing pulses with an increasing value, each one followed by a check of the condition of the transistors; the loop is terminated as soon as all the transistors are erased.
The above-described loop of erasing pulses reduces the number of transistors that are over-erased, and therefore feature a negative threshold voltage (depleted transistors). The depleted transistors are conductive even if they are not selected, so that a current flows through the respective bit line; this may cause a malfunctioning of the flash memory (reading of a false logic value 1 for a selected transistor belonging to a bit line with depleted transistors). Therefore, the depleted transistors are identified and restored to a not-depleted condition by a (soft) programming operation, which raises the threshold voltage of the depleted transistors while maintaining their logic value 1.
A drawback of methods known in the art for erasing the flash memory is that they are quite complex. Particularly, the reading operations (for checking if all the transistors have been erased) cause a high power consumption; this drawback is particularly acute when the flash memory is embodied in a battery-supplied portable device in a contact-less application. Moreover, the repeated checks of the sector and the corresponding loading/unloading of the bit lines and word lines at each switching between an erasing pulse and a reading operation makes the erasing procedure very slow.
The series of erasing pulses of increasing value requires a corresponding number of internal voltages, which must be controlled with accuracy; this affects the structure of the flash memory.
A further drawback is that the electric field applied to the oxide layer of the transistors during each erasing pulse is not constant (in the sense of the erasing pulse being steady while the charge in the floating gate decreases), so a less than optimal operation of the transistors is obtained. On the other hand, it is not possible to envisage a finer resolution of the erasing pulses, because it would require a huge number of internal voltages and reading operations (with the above mentioned problems).
In addition, if at the end of the erasing loop too many depleted transistors are connected to the same bit line, their restoring is very difficult (if not impossible). In fact, the unselected depleted transistors shunt part of the current needed for programming the selected depleted transistor.
A solution proposed in the art for alleviating this drawback consists in biasing the unselected transistors to a negative voltage, so as to ensure that all the unselected transistors are not conductive, even if they are depleted. However, this makes the restoring of the depleted transistors quite different from a standard programming operation, requiring the management of voltages with opposed sign at the same time.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome at least the above-mentioned drawbacks.
Briefly, the present invention provides a method of erasing a flash memory integrated in a chip of semiconductor material and comprising at least one matrix of cells with a plurality of rows and a plurality if columns made in at least one insulated body, the cells of each row being connected to a corresponding work line. The method includes the step of applying a single erasing pulse relative to a selected single one of the at least one body to a selected subset of the word lines for erasing the cells of each corresponding row made in the selected body with no intermediate check of the completion of the erasure.
Moreover, the present invention also provides a corresponding flash memory.
REFERENCES:
patent: 5617359 (1997-04-01), Ninomiya
patent: 6091642 (2000-07-01), Pasotti et al.
patent: 6480419 (2002-11-01), Lee
patent: 6567316 (2003-05-01), Ohba et al.
patent: WO 00/68952 (2000-11-01), None
European Search Report from European patent application No. 01830067 filed Feb. 5, 2001.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Phung Anh
STMicroelectronics S.r.l.
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