Oscillators – Automatic frequency stabilization using a phase or frequency... – With intermittent comparison controls
Patent
1996-04-02
1997-09-02
Mis, David
Oscillators
Automatic frequency stabilization using a phase or frequency...
With intermittent comparison controls
331 1A, 331 20, 331 25, 327156, 327157, 327159, 348536, 360 51, H03L 708
Patent
active
056636881
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND
The invention relates to a method of enhancing the noise immunity of a phase-locked loop used in the field of television signal processing, especially when locking onto the frequency of synchronization signals. The invention relates also to a device comprising a phase-locked loop and implementing the said method.
The invention is intended particularly for phase-locked loops produced as integrated circuits, particularly in MOS technology, more particularly CMOS technology.
A functional diagram of a conventional phase-locked loop is represented in FIG. 1. According to this specific example of the prior art, the PLL receives a reference signal consisting of synchronization pulses derived by a synchronization extractor 1 from the composite video baseband signal, CVBS.
A phase comparator 2 receives the synchronization thus extracted on one of its inputs. A filter 3, as well as a voltage-controlled oscillator (or VCO) 4 are connected in series with the phase comparator 2. The output of the VCO is looped back onto another input of the phase comparator 2. The return loop includes a frequency divider by N, referenced 5.
When the device is locked, the input signals of the phase comparator 2 are in phase, the voltage on the filter 3 does not vary and the output frequency of the VCO is constant. This frequency is equal to N times the frequency of the synchronization.
In the event of a jump in the phase of the synchronization signal coming from the extractor 1 (reference signal), the said synchronization signal and the looped-back signal are no longer in phase. The comparator then causes the voltage on the filter 3 to vary, and consequently the voltage at the input of the VCO 4. The output frequency of the latter then varies in such a way as to put the two input signals of the phase comparator 2 back in phase.
FIG. 2a shows an example of a CVBS signal, as well as two defects 6 and 7 possibly leading to erroneous synchronization pulses being obtained. Such a noisy CVBS signal is encountered in practice, for example at the output of a video recorder.
FIG. 2b represents the signal derived by the synchronization extractor 1 from the CVBS signal represented by FIG. 2a. The defect 6 creates a stray pulse 6a, while the defect 7 causes a pulse to be absent. In both cases, there is unlocking of the PLL loop.
The output frequency of the PLL loop is thus prone to variations. The latter can be troublesome particularly in the following three cases: large even for small variations in voltage at the input of the said VCO. possessing logic outputs as described below, a small phase jump at the input can cause it to trip over. There is no gradation between the high state and the low state of the. PFD outputs. As in the case of high gain of the VCO 4, this can cause rapid variations ("jitter") of the output frequency. variations in the said frequency can occasion malfunctioning.
Such defects are encountered particularly in integrated circuits, for example circuits of the CMOS type.
The purpose of the invention is to avoid the unlocking of a phase-locked loop due to a CVBS signal of mediocre quality. In consequence, one object of the invention is to enhance the noise immunity of a phase-locked loop and to minimize the rapid variations or "jitter" of the output frequency of the phase-locked loop.
The subject of the invention is a method of enhancing the noise immunity of a phase-locked loop, the said phase-locked loop comprising a comparator and means for inhibiting the action of the comparator on the said phase-locked loop, the said method being characterized in that the said inhibition is lifted in the course of a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop and of a second time window derived from the loop return signal.
In what follows, the term "reference signal" refers to the signal to the frequency of which it is desired to lock the PLL loop. It relates therefore to the signal sent to the comparator of the said loop.
The term "input signal"
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Dell'ova Francis
Delmas Christian
Paillardet Frederic
Emanuel Peter M.
Mis David
Thomson Multimedia S.A.
Tripoli Joseph S.
Wein Frederick A.
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