Method of enhanced fill of vias and trenches

Details Method of enhanced fill of vias and trenches Method of enhanced fill of vias and trenches

2001-06-12

2003-03-18

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S762000, C438S677000

Reexamination Certificate

active

06534865

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to integrated circuits and more particularly to controlling interconnect channel thickness therein.
BACKGROUND ART
In the manufacture of integrated circuits, after the individual devices such as the transistors have been fabricated in and on the semiconductor substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally called “metallization” and is performed using a number of different photolithographic, deposition, and removal techniques.
In one interconnection process, which is called a “dual damascene” technique, two interconnect channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes perpendicular to each other and interconnected by a vertical connection, or “via”, at their closest point. The dual damascene technique is performed over the individual devices which are in a device dielectric layer with the gate and source/drain contacts extending up through the device dielectric layer to contact one or more channels in a first channel dielectric layer.
The first channel formation of the dual damascene process starts with the deposition of a thin first channel stop layer. The first channel stop layer is an etch stop layer which is subject to a photolithographic processing step which involves deposition, patterning, exposure, and development of a photoresist, and an anisotropic etching step through the patterned photoresist to provide openings to the device contacts. The photoresist is then stripped. A first channel dielectric layer is formed on the first channel stop layer. Where the first channel dielectric layer is of an oxide material, such as silicon oxide (SiO
2
), the first channel stop layer is a nitride, such as silicon nitride (SiN), so the two layers can be selectively etched.
The first channel dielectric layer is then subject to further photolithographic process and etching steps to form first channel openings in the pattern of the first channels. The photoresist is then stripped. An optional thin adhesion layer is deposited on the first channel dielectric layer and lines the first channel openings to ensure good adhesion of subsequently deposited material to the first channel dielectric layer.
For conductor materials such as copper, which are deposited by electroplating, a seed layer is deposited on the barrier layer and lines the barrier layer in the first channel openings to act as an electrode for the electroplating process. Processes such as electroless, physical vapor, and chemical vapor deposition are used to deposit the seed layer.
A first conductor material is deposited on the seed layer and fills the first channel opening. The first conductor material and the seed layer generally become integral, and are often collectively referred to as the conductor core when discussing the main current-carrying portion of the channels.
A chemical-mechanical polishing (CMP) process is then used to remove the first conductor material, the seed layer, and the barrier layer above the first channel dielectric layer to form the first channels. An abrasiveless chemical is used for the chemical-mechanical polishing process in order to prevent abrasives from being left in the channel. When a layer is placed over the first channels as a final layer, it is called a “capping” layer and a “single” damascene process is completed. When the layer is processed further for placement of additional channels over it, the layer is a via stop layer.
The via formation step of the dual damascene process starts with the deposition of a thin via stop layer over the first channels and the first channel dielectric layer. The via stop layer is an etch stop layer which is subject to photolithographic processing and anisotropic etching steps to provide openings to the first channels. The photoresist is then stripped.
A via dielectric layer is formed on the via stop layer. Again, where the via dielectric layer is of an oxide material, such as silicon oxide, the via stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched. The via dielectric layer is then subject to further photolithographic process and etching steps to form the pattern of the vias. The photoresist is then stripped.
A second channel dielectric layer is formed on the via dielectric layer. Again, where the second channel dielectric layer is of an oxide material, such as silicon oxide, the via stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched. The second channel dielectric layer is then subject to further photolithographic process and etching steps to simultaneously form second channel and via openings in the pattern of the second channels and the vias. The photoresist is then stripped.
An optional thin adhesion layer is deposited on the second channel dielectric layer and lines the second channel and the via openings. A barrier layer is then deposited on the adhesion layer and lines the adhesion layer in the second channel openings and the vias. Again, for conductor materials such as copper and copper alloys, a seed layer is deposited by electroless deposition on the barrier layer and lines the barrier layer in the second channel openings and the vias.
A second conductor material is deposited on the seed layer and fills the second channel openings and the vias.
A CMP process is then used to remove the second conductor material, the seed layer, and the barrier layer above the second channel dielectric layer to form the first channels. When a layer is placed over the second channels as a final layer, it is called a “capping” layer and the “dual” damascene process is completed.
The layer may be processed further for placement of additional levels of channels and vias over it. Individual and multiple levels of single and dual damascene structures can be formed for single and multiple levels of channels and vias, which are collectively referred to as “interconnects”.
The use of the single and dual damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum (Al) to other metallization materials, such as copper, which are very difficult to etch.
A major problem occurs in this process is related to the lengthy process of forming a barrier layer, copper seed layer, and copper conductor core. Physical vapor deposition of the barrier layer and the copper seed layer is very non-conformal, meaning that it does not conform in a uniform manner to the surface of the dielectric layer on which it is deposited. Other layers, such as the copper conductor layer, are more conformal and is deposited using electroplating. This becomes a problem due to the filling profile, or the shape of the area in which the copper is to be filled. This filling profile, which is common to trenches, channels, and vias where copper is used as a conductor material, is such that the copper seed layer is deposited more rapidly on the exposed flat, horizontal surfaces than on the vertical surfaces. Filling trenches, channels, and vias too rapidly then can cause voids to be formed in the copper conductor core leading to reduced conductivity in the current-carrying connections.
Finding a way to change the filling profile so that, despite the non-conformity of copper seed layer, the copper conductor core can be deposited quickly and without voids forming has been long sought but has long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a manufacturing method and apparatus for filling vias and trenches in integrated circuits having a semiconductor substrate with a semiconductor device provided thereon. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening provided therein. A barrier layer lines the channel opening. A seed layer is deposited over the bar

Affiliated with

Also associated with

Rating

Method of enhanced fill of vias and trenches does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of enhanced fill of vias and trenches, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of enhanced fill of vias and trenches will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3084446