Method of engaging electrically conductive test pads on a semico

Details Method of engaging electrically conductive test pads on a semico Method of engaging electrically conductive test pads on a semico

1997-10-31

2000-09-26

Ballato, Josie

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324755, 324757, 324765, G01R 3102, G01R 3126

Patent

active

061247219

ABSTRACT:
A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

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Moto'o Nakano, "A Probe for Testing Semiconductor Integrated Circuits and a Test Method Using said Probe," Mar. 25, 1991, Japanese Patent Office Disclosure No. Hei 3-69131, filing No. Hei 1-205301, filing date Aug. 8, 1989.

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