Method of enabling alignment of wafer in exposure step of IC...

Details Method of enabling alignment of wafer in exposure step of IC... Method of enabling alignment of wafer in exposure step of IC...

2011-02-01

2011-02-01

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

C257SE23114

Reexamination Certificate

active

07880274

ABSTRACT:
A method of enabling alignment of a wafer in at least one exposure step of an integrated circuit process after a UV-blocking metal layer is formed over the whole wafer covering a patterned upmost metal layer of the integrated circuit is described, wherein the wafer has an edge portion where a composite dielectric layer corresponding to the dielectric layers of the integrated circuit is formed. The method includes forming a cavity in the composite dielectric layer over the edge portion of the wafer in the patterning process of the upmost metal layer, such that an alignment mark is formed after the UV-blocking metal layer is formed.

REFERENCES:
patent: 5401691 (1995-03-01), Caldwell
patent: 6010945 (2000-01-01), Wu
patent: 6180537 (2001-01-01), Tseng

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