Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-11-01
2002-09-24
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S694000
Reexamination Certificate
active
06455430
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of forming an interconnection used in a semiconductor device, and particularly to a method of forming an embedded interconnection by a damascene method using copper.
2. Description of the Related Art
Attention has been given to Cu as the next-generation wiring material as an alternative to an aluminum wire or interconnection. This is because excellent electromigration resistance is obtained while it has of course a low resistance of 1.69×10
−6
ohmcm. Two processing methods: Chemical Mechanical Polishing (hereinafter called “CMP”) and Reactive Ion Etching are considered to form a Cu interconnection. Since, however, it is difficult to apply the conventional RIE method to the formation of the Cu interconnection because Cu halide is low in vapor pressure, the formation of a damascene interconnection using CMP is now mainstream.
However, CMP used for Cu has a big problem in that 1) a dent or recess defined in a wired portion by chemical etching through an oxidizing agent in a polishing solution, 2) thinning of an interconnection, which is developed due to the cutting of an insulating film, which is called “dishing”, and 3) etc. occur. The recess described in the paragraph
1
) can be improved by the optimization of the ratio of mixture of a slurry and an oxidizing agent. The thinning described in the paragraph
2
) can be improved by selecting the optimal abrasive cloth. However, the trouble described in the paragraph
3
) results from the fact that since the polishing speed of Cu within a wafer surface is non-uniform, Cu and an interlayer insulating film must be overpolished at their given portions. It was therefore difficult to solve such a problem.
SUMMARY OF THE INVENTION
The present invention provides a method of depositing Cu and a C (carbon) film having a high selection ratio over an interlayer insulating film and thereafter defining a contact hole therein, forming Cu over an entire surface including the contact hole, polishing Cu by CMP, terminating the polishing of Cu by a stopper film of the C film, and forming an embedded interconnection in the contact hole.
An object of the present invention is to deposit Cu and a material having a high selection ratio over an interlayer insulating film thereby to restrain the occurrence of thinning of Cu upon CMP and provide a damascene Cu interconnection processed with high accuracy.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.
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Oki Electric Industry Co. Ltd.
Utech Benjamin L.
Vinh Ian
Volentine & Francos, PLLC
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