Stock material or miscellaneous articles – All metal or with adjacent metals – Composite; i.e. – plural – adjacent – spatially distinct metal...
Reexamination Certificate
2000-06-13
2001-09-18
Jones, Deborah (Department: 1775)
Stock material or miscellaneous articles
All metal or with adjacent metals
Composite; i.e., plural, adjacent, spatially distinct metal...
C428S209000, C428S670000, C428S673000, C428S674000, C257S750000, C257S751000, C257S763000
Reexamination Certificate
active
06291082
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices and techniques for their manufacture, and more particularly, to semiconductor devices and manufacturing techniques for encapsulating interconnect structure that has been fabricated of copper.
2. Discussion of the Related Art
Typically, in the manufacture of high-density semiconductor devices, multiple layers of conductive material connected by vias or plugs are provided above a substrate. Such multiple layers, typically of metal, are employed in order to accommodate high device densities. While aluminum has been used mainly in the past for metallization within integrated circuits, as metal lines are scaled down to smaller dimensions (including decreasing widths), the problem of failure due to electromigration, which may lead to open or shorted metal lines, has become significant. Additionally, as dimensions of metal lines further decrease, metal line resistance increases, and this increase may adversely affect circuit performance.
Presently, the use of copper in interconnect structure is receiving great attention, because copper has lower bulk resistivity than aluminum and potentially higher electromigration tolerance than aluminum.
With damascene dimensions of conductors decreasing below 0.1 micron in width or diameter, the aspect ratio of a copper interconnect may well exceed 5:1. In such a situation, when forming a copper interconnect by electroplating, a highly conformal and low-resistivity base layer is needed prior to such formation. A currently used ion metal plasma (IP) base layer contains both a high resistivity barrier layer (for example Ta or TaN) and a copper seed layer with relatively high resistance (due to the effect of increased thin-film resistance with decreasing thickness), leading to circuit performance problems as discussed above. Furthermore, such a base later has low conformality and extendability when applied to small features, so that voids are readily formed in high aspect ratio trench/vias.
Therefore, what is needed is a method for providing high conformality of a base layer in a copper electroplating process, meanwhile providing for high conductivity and high electromigration resistance of the copper metallization.
SUMMARY OF THE INVENTION
A dielectric layer is provided over a metal line and has via opening which communicates with the metal line. A layer of silver is deposited over the structure and into the via opening, providing close conformance within the opening. A resist layer is provided over the resulting structure and a trench opening is provided therein which communicates with the via opening defined by the dielectric layer. Copper is then deposited by electroplating in the trench/via openings, and the resist material is removed, leaving some of the copper extending beyond the dielectric layer. Another layer of silver is deposited over the resulting structure, providing close conformance with the extended portion of the copper, and in contact with extended portions of the first-mentioned silver layer. An anneal operation is undertaken, and portions of the silver layers are selectively removed, leaving a copper trench/via structure encapsulated by copper-silver alloy.
As an alternative, after formation of a trench/via opening in a dielectric layer, a seed layer containing palladium is formed on the dielectric surface in the opening prior to deposition of the silver layer in the opening. Then, copper is deposited by electroplating, and after a chemical mechanical polish of metals from the dielectric surface, a seed layer containing palladium is formed only over exposed metal surfaces. Next, a silver layer is deposited only over exposed metal surfaces, and an anneal step is undertaken so that the copper trench/via structure is encapsulated by copper-silver alloy.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there are shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5824599 (1998-10-01), Schacham-Diamand et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 6022808 (2000-02-01), Nogami et al.
patent: 6100194 (2000-08-01), Chan et al.
patent: 6136707 (2000-10-01), Cohen
patent: 6197688 (2001-03-01), Simpson
Silver Metallization for Advanced Interconnects, Manepalli et al., IEEE Transactionson Advanced Packaging, vol. 22, No. 1, Feb. 1999.
Advanced Micro Devices , Inc.
Jones Deborah
Stein Stephen
Winters Paul J.
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