Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Involving measuring – analyzing – or testing
Reexamination Certificate
2006-11-09
2010-12-14
Olsen, Kaj K (Department: 1795)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Involving measuring, analyzing, or testing
C205S081000, C205S103000, C205S105000, C205S107000, C205S123000, C205S125000
Reexamination Certificate
active
07850836
ABSTRACT:
An initial pulse current cycle is supplied to at least one through-hole via. The pulse current cycle includes a forward pulse current. The magnitude of the forward pulse current is lower than the magnitude of the reverse pulse current. A corresponding forward and reverse current density is generated across the via causing conductive material to be deposited within the via, thereby reducing the effective aspect ratio of the via. At least one subsequent pulse current cycle is supplied. The magnitudes of the forward and reverse pulse currents of the subsequent pulse current cycle are determined in relation to the reduced effective aspect ratio. A subsequent corresponding forward and reverse current density is generated across the through-hole via causing conductive material to be deposited within the via, thereby further reducing the effective aspect ratio of the via.
REFERENCES:
patent: 4830987 (1989-05-01), Miller et al.
patent: 5972192 (1999-10-01), Dubin et al.
patent: 6340633 (2002-01-01), Lopatin et al.
patent: 2002/0022318 (2002-02-01), Choi
patent: 2003/0019755 (2003-01-01), Hey et al.
patent: 2003/0221967 (2003-12-01), Tsuchida et al.
patent: 0251347 (1988-07-01), None
Lin, C. J., et al., “High Density and Through-Wafer Copper Interconnects and Solder Bumps for MEMS Wafer-Level Packaging”, Microsystem Technologies, 10, 517-521 (2004).
Seong, J. O., et al., “High Density, High Aspect Ratio Through-Wafer Electrical Interconnect Vias for MEMS Packaging”, IEEE Transactions on Advanced Packaging, IEEE Transactions on Advanced Packaging, 26, 302-309 (2003).
Kutchoukov, V. G., et al., “Through-Wafer Interconnect Technology for Silicon”, Journal of Micromechanics and Microengineering, 14, 1029-1036 (2004).
Nguyen, N. T., et al., “Through-Wafer Copper Electroplating for Three-Dimensional Interconnects”, Journal of Micromechanics and Microengineering, 12, 395-399 (2002).
Chow, Eugene M., et al., “Process Compatible Polysilicon-Based Electrical Through-Wafer Interconnects in Silicon Substrates” Journal of Microelectromechanical systems, 11, 631-640 (2002).
Christensen, Carsten., et al. “Wafer Through-Hole Interconnections with High Vertical Wiring Densities”, IEEE Transaction on Components, Packaging and Manufacturing Technology- Part A, 19, 516-522 (1996).
Hyongsok, T. Soh., et al., “Ultra-Low Resistance, Through-Wafer Via (TWV) Technology and Its Applications in Three Dimensional Structures on Silicon”, Japanese Journal of Applied Physics, 38, 2393-2396 (1999).
Burkett, S.L., et al., “Advanced Processing Techniques for Through-Wafer Interconnects,” 22 J. Vacuum Science and Tech. B, 248-256 (2004).
Jian-Jun, Sun, et al., “High-Aspect-Ratio Copper Vla Filling Used for Three Dimensional Chip Stacking”, Journal of the Electrochemical Society, 150 (6), G355-G358 (2003).
Dixit Pradeep
Miao Jianmin
Crockett & Crockett
Crockett, Esq. K. David
Nanyang Technological University
Olsen Kaj K
Syrengelas, Esq. Niky Economy
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