Method of electrically testing a packaging structure having n in

Details Method of electrically testing a packaging structure having n in Method of electrically testing a packaging structure having n in

1983-07-29

1985-01-15

Strecker, Gerard R.

Electricity: measuring and testing

Plural, automatically sequential tests

G01R 3128, G06F 1100

Patent

active

044940661

ABSTRACT:
Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package. The intent of the design rules is to design chips such that each chip can be "isolated" for testing purposes through the pins (or other contacts) of a higher level package containing such chips. It is also required that the "Level Sensitive Scan Design" (LSSD) discipline, or rules, be followed for each chip and for the package clock distribution network. Further, the LSSD Rules which ensures the capability of scanning data into and out of the package SRLs (shift register latches) must be satisfied for the total package.

REFERENCES:
patent: 3789205 (1974-01-01), James
patent: 4183460 (1980-01-01), Yuen et al.
patent: 4220917 (1980-09-01), McMahon
patent: 4241307 (1980-12-01), Hong
patent: 4395767 (1983-07-01), Van Brunt et al.

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