Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2004-11-04
2008-08-12
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S060000
Reexamination Certificate
active
07411570
ABSTRACT:
One field time period is formed of a plurality of subfields having at least a writing time period and a sustaining time period, of an initialization time period, the writing time period, and the sustaining time period. A display electrode pair is divided into a plurality of blocks. Starting timings of the subfields of the blocks are set to be shifted so that writing timings of two or more blocks of the plurality of blocks do not coincide with each other.
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M. Ishii et al., “43.2: Driving of PDPs with 208 Sub-Fields Using a Grouped Address-While-Display Scheme”, SID International Symposium Digest of Technical Papers, vol. XXXII, Jun. 2001, pp. 1134-1137.
Kawase Toru
Nakakita Tomoki
Abdin Shaheda A
Hjerpe Richard
Matsushita Electric - Industrial Co., Ltd.
Wenderoth , Lind & Ponack, L.L.P.
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