Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-11-06
2004-06-29
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S063000, C345S068000
Reexamination Certificate
active
06756950
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of driving a plasma display panel (hereinafter referred to as PDP) and its apparatus. The method and apparatus of the present invention can reduce the backglow phenomena caused by the discharge operation during the reset period for PDP.
2. Description of Prior Art
The PDP displays images by means of charges accumulated through electrode discharge. It is one of the most interesting plate display devices because, among other advantages, it can provide a large screen aspect ratio and can display full-color images. The basic theory and operation of a PDP is described below.
FIG. 1
is a cross-sectional view of a conventional PDP cell constructed by two glass substrates
1
and
7
and the components formed thereon. Inactive gas, such as Ne, Xe, is filled in the cavity between the glass substrates
1
and
7
. The components formed on the glass substrate
1
include sustaining electrodes X, scan electrodes Yi which are parallel to each other, a dielectric layer
3
and a protective film
5
. The components formed on the glass substrate
7
include address electrodes Ai and the fluorescent material
9
formed thereon. The partition wall
8
is formed on the peripheral of each PDP cell to isolate the PDP cell. Therefore, each PDP cell
10
includes three kinds of electrodes, i.e., the sustaining electrodes and the scan electrodes which are parallel to each other, and the address electrodes Ai crossing the sustaining electrodes and the scan electrodes.
FIG. 2
is a block diagram illustrating a plasma display formed by the PDP cells shown in FIG.
1
. As shown in the drawing, the PDP
100
is driven by the scan electrodes Y
1
~Yn, the sustaining electrodes X and the address electrodes A
1
~Am. The position of the cell
10
is as shown in the drawing. Each, cell is isolated by the partition wall
8
as shown in FIG.
1
. Furthermore, the plasma display includes the control circuit
110
, the Y scan driver
112
, the X sustaining driver
114
and the address driver
116
. The control circuit
110
generates timing signals for the drivers according to the external clock signal CLOCK, the data signal DATA, the vertical synchronous signal VSYNC and the horizontal synchronous signal HSYNC, wherein the clock signal CLOCK represents the data transmittal clock, the data signal DATA represents the display data, and the vertical synchronous signal VSYNC and the horizontal synchronous signal HSYNC are respectively used to define the timing sequences of a frame and a scanning line. The control circuit
110
sends the display data and the clock signal to the address driver
116
and sends the corresponding frame control clock to the Y scan driver
112
and the sustaining driver
114
. The display data is transmitted to the address driver
116
by the control circuit
110
and is written to each cell through the address electrodes A
1
~Am while the Y scan driver
112
sequentially scans the scan electrodes Y
1
~Yn. The detailed operation and the control signals for the electrodes are described below.
FIG. 3
is a diagram illustrating the manner to drive a conventional PDP to display a frame. As shown in the drawing, each frame is divided into eight sub-fields SF
1
~SF
8
. However, the sub-field is different to the field of a conventional cathode ray tube (CRT), which displays an image by respectively scanning the odd scanning lines and the even scanning lines. The PDP field displays various gray scales for all of the scanning lines. Each sub-field includes three operating period, that is, the reset period R
1
~R
8
, the address period A
1
~A
8
and the sustain period S
1
~S
8
. The reset period is used to clear the residual charges of the last field display and a certain amount of the wall charges left in each cell. The address period is used to accumulate wall charges into the cell, which is to be displayed (i.e., turned ON), through address discharge. The sustain period is to sustain discharge for displaying in the cell which has accumulated charges through the address discharge. All of the PDP cells are processed at the same time during the reset period R
1
~R
8
and the sustain period S
1
~S
8
. The address operation is sequentially performed for each cell on the scan electrodes Y
1
~Yn during the address period A
1
~A
8
. Moreover, the display brightness is proportional to the length of the sustain period S
1
~S
8
. In the example of
FIG. 3
, the length of the sustain periods S
1
~S
8
of the sub-fields SF
1
~SF
8
can be set in a ratio of 1:2:4:8:16:32:64:128 to display images in 256 gray scales.
FIG. 4
is a timing diagram of the control signals on the electrodes in a single sub-field of the prior art. The signals on the address electrodes Ai are generated by the address driver
116
, the signals on the sustaining electrodes X are generated by the X sustaining driver
114
, and the signals on the scan electrodes Y
1
~Yn are generated by the scan driver
112
. As shown in the drawing, each sub-field includes the reset period, the address period and the sustain period. The waveform of the signals in each period and the resulted manners are described in detail below.
At the time point a (in
FIG. 4
) of the reset period, the voltage of the scan electrodes Y
1
~Yn is set to 0 V, and a write pulse having a voltage of VS+VW is applied to the sustaining electrode X, in which the voltage VS+VW is larger than the discharge start voltage between the sustaining electrode X and the scan electrode Yi. Therefore, the global writing discharge W occurs between the sustaining electrode X and the scan electrodes Yi. This discharge process accumulates negative charges on the sustaining electrode X and positive charges on the scan electrodes Yi. The electric field produced by the accumulated negative charges and the positive charges will cancel out the voltage drop between the sustaining electrodes, thus the time of global writing discharge W is very short.
At the time point b, the sustaining electrode X is set to 0 V, and a sustaining pulse
202
having a voltage of V
s
is applied to all of the scan electrodes Y
1
~Yn, wherein the value of the voltage V
s
plus the voltage caused by the charges accumulated between the sustaining electrodes must be larger than the discharge start voltage between the scan electrodes Yi and the sustaining electrode X. Thus, the total sustaining discharge S occurs between the sustaining electrode X and the scan electrodes Yi. Different from the previous discharge process, this discharge process accumulates positive charges on the sustaining electrode X and negative charges on the scan electrodes Yi.
At the time point c, the scan electrode Yi is set to 0 V, an erase pulse
203
having a voltage lower than V
s
is applied to the sustaining electrode X, and an address pulse having a voltage of −V
s
can be applied to the address electrode Ai. The erase pulse is used to neutralize a part of the charges. On the scan electrodes Y
1
~Yn, required wall charges are left so that the write operation can proceed with a lower voltage in the sequential address period.
In the address period, the voltage of the sustaining electrode X and the scan electrodes Yi are pulled up to V
s
at the time point d. Then a scan pulse
204
is sequentially applied to the scan electrodes Y
1
~Yn from the time point e, and an address pulse having a voltage of V
A
is applied to the address electrode Ai at the same time. When a cell of a scanning line turns ON, the write discharge occurs, that is, the corresponding display data is written into the cell.
After scanning all of the scan electrodes Y
1
~Yn, the sustain period begins. The sustaining electrode X and the scan electrode Yi are first set to 0 V. Then the sustaining pulses
205
having the same voltage are applied to the sustaining electrode X and the scan electrodes Yi in an alternate way, i.e., at the time point f and at the time point g. Thus, the cell with the data ON during the address period will irradiate. It should be noted that the waveform of
Lo Lih Shang
Tsai Andy T K
Au Optronics Corp.
Chow Dennis-Doon
Ladas & Parry
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