Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-08-07
2004-01-13
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C315S169400
Reexamination Certificate
active
06677921
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Korean Application No. 2000-55476, filed Sep. 21, 2000, in the Korean Industrial Property Office, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a three-electrode surface-discharge plasma display panel.
2. Description of the Related Art
FIG. 1
shows a structure of a conventional three-electrode surface-discharge plasma display panel, and
FIG. 2
shows an electrode line pattern of the plasma display panel shown in FIG.
1
. Referring to
FIGS. 1 and 2
, address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
, dielectric layers
11
and
15
, Y electrode lines Y
1
, Y
2
, . . . . Y
n
, X electrode lines X
1
, X
2
, . . . , and X
n
, phosphors
16
, partition walls
17
, and an MgO protective film
12
are provided between front and rear glass substrates
10
and
13
of a conventional surface-discharge plasma display panel
1
.
The address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
are coated over the front surface of the rear glass substrate
13
in a predetermined pattern. The lower dielectric layer
15
is coated over the entire front surface of the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
. The partition walls
17
are formed on the front surface of the lower dielectric layer
15
to be parallel to the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
. The partition walls
17
define discharge areas of the respective pixels and prevent optical crosstalk among pixels. The phosphors
17
are coated between partition walls
17
.
The X electrode lines X
1
, X
2
, . . . X
n
and the Y electrode lines Y
1
, Y
2
, . . . Y
n
are arranged on the rear surface of the front glass substrate
10
in a predetermined pattern so as to be orthogonal to the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
. The respective intersections define corresponding pixels. The X electrode lines X
1
, X
2
, . . . and X
n
and the Y electrode lines Y
1
, Y
2
, . . . Y
n
each comprise conductive indium tin oxide (ITO) electrode lines (X
na
and Y
na
of
FIG. 2
) and metal bus electrode lines (X
nb
and Y
nb
of FIG.
2
). The upper dielectric layer
11
is coated over the entire rear surface of the X electrode lines X
1
, X
2
, . . . X
n
and the Y electrode lines Y
1
, Y
2
, . . . Y
n
. The MgO protective film
12
protects the panel
1
against strong electrical fields and is coated over the entire rear surface of the upper dielectric layer
11
. A gas to form a plasma is hermetically sealed in a discharge space
14
.
The above-described plasma display panel is basically driven such that a reset step, an address step, and a display step are sequentially performed in a unit subfield. In the reset step, wall charges remaining in the previous subfield are erased and space charges are evenly formed. In the address step, the wall charges are formed in a selected pixel area. In the display step, light is produced at the pixel at which the wall charges are formed in the address step. In other words, if alternating pulses of a relatively high voltage are applied between the X electrode lines X
1
, X
2
, . . . X
n
and the Y electrode lines Y
1
, Y
2
, . . . Y
n
, a surface discharge occurs at the pixels at which the wall charges are formed. The plasma is formed at the gas in the discharge space
14
, and the phosphors
16
are excited by ultraviolet rays to thus emit the light.
In the above-described driving method, in order to perform gray scale display on a plasma display panel, a time-divisional driving method is used in which a frame, which is a unit display period, is divided into subfields, each subfield having different display times to display gray scales. For example, when displaying 256 gray scales by 8-bit image data in units of frames, 8 subfields are set to each frame (in the case of a sequential driving method) or field (in the case of a non-interlaced driving method). Here, according to the method of arranging the respective subfields on a unit display period, there are an address-display separation driving method and an address-while-display driving method.
According to the address-display separation driving method, since the time regions of the respective subfields are separated in a unit display period, the time regions of an address period and a display period are also separated in each subfield. Thus, in an address period, a pair of X and Y electrode lines must wait until the other pairs of X and Y electrode lines are all addressed even after the pertinent pair of X and Y electrode lines are addressed. Thus, the time for the address period increases for each subfield, which relatively reduces the time for a display period. Although the address-display separation driving method is advantageous in that the driving circuit and algorithm are simple, the luminance of a plasma display panel driven based on this method is disadvantageously low.
According to the address-while-display driving method, since the time regions of the respective subfields overlap in a unit display period, the time regions of the address and display periods in the respective subfields also overlap. Thus, immediately after addressing of each pair of X and Y electrode lines is performed in an address period, a display discharge step is performed. Since the time for the address period of each subfield is reduced, the display period is relatively increased. Although the address-while-display driving method is disadvantageous in that the driving circuit and algorithm are complex, the luminance of light emitted from a plasma display panel driven based on this method is advantageously increased.
SUMMARY OF THE INVENTION
To solve the above and other problems, it is an object of the present invention to provide a method of driving a plasma display panel which can reduce the number of driving devices of X and Y driving circuits and can enhance the luminance of the light emitted from the plasma display panel by using an address-while-display driving method.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Accordingly, to achieve the above and other objects, there is provided a method of driving a plasma display panel according to an embodiment of the present invention, the plasma display panel having front and rear substrates disposed opposite each other, X and Y electrode lines formed parallel to each other between the front and rear substrates, and address electrode lines formed orthogonal to the X and Y electrode lines to define corresponding a discharge cell at interconnections, where the X electrode lines are divided into X groups and the Y electrode lines are divided into Y groups such that no two adjacent pairs of adjacent X and Y electrode lines belong to the same pair of X and Y groups and the X and Y electrode lines of the respective X and Y groups are commonly connected to be driven, and at least first and second subfields are driven in an overlapping manner to display gray scales during a unit display period, the method includes a scan operation to form wall charges around a first pair of X and Y electrode lines for a first subfield, an address operation to erase wall charges as non-selected discharge cells, a display operation to generate light at selected discharge cells in the subfield, a second driving operation of performing the scan, address, and display operations for a second pair of X and Y electrode lines of a second subfield at different timing points, and a repetition operation of performing the scan, address, display, and second driving operations for the remaining pairs of X and Y electrode lines of the first and second subfields.
According to an aspect of the present invention, the scan operation includes applying a Y scan pulse of a
Igarashi Kiyoshi
Ishii Makoto
Jung Nam-sung
Kang Kyoung-ho
Kim Hee-Hwan
McGuireWoods LLP
Said Mansour M.
Samsung SDI & Co., Ltd.
Shankar Vijay
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