Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-04-20
2003-09-02
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S068000, C345S690000
Reexamination Certificate
active
06614413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving a plasma display panel (hereinafter abbreviated as the “PDP”) of a matrix display type.
2. Description of Related Art
As a display panel of the matrix display type, an AC (alternate current discharge) type PDP is known.
The AC-type PDP comprises a plurality of column electrodes (address electrodes) and a plurality of row electrode pairs arranged orthogonal to the column electrodes, with each pair of row electrodes forming a scanning line. The row electrode pairs and column electrodes are covered with a dielectric layer to separate them from a discharge space. At an intersection of a row electrode pair with a column electrode, a discharge cell is formed corresponding to one pixel.
As a method of displaying a half-tone image on such a PDP, a so-called subfield method is described, for example, in Japanese Patent Kokai No. 4-195087. In the subfield method, a field period is divided into N subfields, in each of which light is emitted for a time corresponding to weighting applied to an associated bit of N-bit pixel data.
FIG. 1
illustrates a light emission driving format in one field period according to the subfield method.
In the example illustrated in
FIG. 1
, supplied pixel data is assumed to be 6-bit data, and one field period is divided into six subfields SF
1
, SF
2
, . . . , SF
6
for driving light emission. A gradation display of 64 steps can be achieved for an image of one field by executing light emission throughout the six subfields.
Each subfield includes a simultaneous resetting stage Rc, a pixel data writing stage Wc and a light emission sustaining stage Ic. In the simultaneous resetting stage Rc, all discharge cells in the PDP are simultaneously excited to discharge (reset discharge) to form a wall charge uniformly in each of all discharge cells. In the next pixel data writing stage Wc, a selective erasing discharge is excited in accordance with pixel data in each discharge cell. In this event, the wall charge in a discharge cell which undergoes the erasure discharge is extinct to become a “non-light emitting cell.” On the other hand, a discharge cell which does not undergo the erasure discharge has the wall charge maintained, so that it serves as a “light emitting cell.” In the light emission sustaining stage Ic, the light emitting cells are maintained in a discharge light emitting state for a time corresponding to weighting of each subfield. In this way, the emitted light is sustained in the respective subfields SF
1
-SF
6
in a light emitting period ratio of 1:2:4:8:16:32 in order.
When a selective erasure address method is employed for selectively erasing a wall charge formed in each of the discharge cells as mentioned above in the pixel data writing stage Wc, the simultaneous resetting stage Rc, indicated by hatchings in
FIG. 1
, is essentially provided at the head of each subfield.
However, the reset discharge performed for all discharge cells in the simultaneous resetting stage Rc involves relatively strong discharge, i.e., emission of light at a high luminance level. Thus, since the reset discharge causes light emission at the six times indicated by hatchings in
FIG. 1
without any relation to pixel data, this results in a problem of degraded contrast in images.
Also, in the driving manner illustrated in
FIG. 1
, for example, a discharge cell which emits light at a luminance level
31
has a light emitting pattern reverse to that of a discharge cell which emits light at a luminance level
32
. In other words, one cell is emitting light, while the other cell is not, thus causing a problem that a pseudo-contour is formed on the boundary of the two discharge cells.
Further, a reduction in power consumption is currently a general challenge in commercializing such PDP.
OBJECT AND SUMMARY OF THE INVENTION
The present invention has been made to solve the problems mentioned above, and its object is to provide a method of driving a plasma display panel which is capable of improving contrast, reducing power consumption, and preventing a pseudo-contour.
To achieve the above object, the present invention provides a method of driving a plasma display panel for driving a plasma display panel having a discharge cell corresponding to one pixel at each intersection of each of a plurality of row electrodes arranged to form each scanning line with each of a plurality of column electrodes crossing with the row electrodes, and the method comprises the steps of dividing a display period of one field into a plurality of subfields, and executing, in each of the subfields, a pixel data writing stage for selectively erasing or discharging a wall charge formed in each of the discharge cells in accordance with display pixel data to set the discharge cells to a light emitting cell or a non-light emitting cell, and a light emission sustaining stage for sustaining only the light emitting cells to emit light for a time corresponding to weighting to the subfield, and executing a simultaneous resetting stage for simultaneously resetting to discharge all the discharge cells to form a wall charge in each of the discharge cells only in the first subfield of a group of subfields, including at least two mutually consecutive subfields of the subfields, wherein the erasing discharge is performed only in the pixel data writing stage in any subfield of the group of subfields.
According to another aspect of the present invention, the display period of one field is divided to N (N is a natural number) subfields, and a subfield group of consecutive M (2≦M≦N) subfields is formed. The method executes in order, a resetting stage for producing a discharge to initialize all of the discharge cells to a state of either of a light emitting cell or a non-light emitting cell only in the subfields in the head portion of the subfield group, a pixel data writing stage for applying to the column electrodes a first pixel data pulse which produces a discharge to set the discharge cells as the non-light emitting cell or the light emitting cell in one of the subfields in the subfield group, and applying to the column electrodes a second pixel data pulse which is the same as the first pixel data pulse in at least one of the subfields existing behind in the subfield group, and a light emission sustaining stage for producing a discharge for causing only discharge cells set as the light emitting cell in each of said subfield to emit light for a light emitting period corresponding to the weighting of the subfield.
REFERENCES:
patent: 6052112 (2000-04-01), Tanaka et al.
patent: 6091398 (2000-07-01), Shigeta
patent: 6097358 (2000-08-01), Hirakawa et al.
patent: 6144364 (2000-11-01), Otobe et al.
patent: 0 782 167 (1997-07-01), None
patent: 0 836 171 (1998-04-01), None
patent: 2 740 253 (1997-04-01), None
patent: 0836171 (1998-04-01), None
Shigeta Tetsuya
Suzuki Masahiro
Tokunaga Tsutomu
Dinh Duc Q.
Hjerpe Richard
Pioneer Electronic Corporation
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