Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2002-05-29
2003-09-23
Wong, Don (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169400, C345S067000, C345S063000
Reexamination Certificate
active
06624588
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving a plasma display panel.
2. Description of the Related Art
In recent years, a variety of thin display devices have been brought into practical use in response to demands for thinner display devices with the trend of increase in screen sizes thereof. A plasma display panel of AC discharge type has drawn attention as one of thin display devices.
FIG. 1
is a diagram generally illustrating the configuration of a plasma display device which comprises a plasma display panel as mentioned above, and a driver for driving the plasma display panel.
In
FIG. 1
, a PDP
10
as a plasma display panel comprises m column electrodes D
1
-D
m
as data electrodes, and n each of row electrodes X
1
-X
n
and Y
1
-Y
n
which are arranged to intersect with each of the column electrodes. A pair of row electrodes X
i
(1≦i≦n) and Y
i
(1≦i≦n) in these row electrodes X
1
-X
n
and Y
1
-Y
n
bear each of display lines on the PDP. These column electrodes D and row electrodes X, Y are disposed in opposition to each other with an intervening discharge space which is filled with a discharge gas, and a discharge cell carrying a pixel is formed at each of intersections of the row electrode pairs and column electrode, including this discharge space. The discharge cell can only take two states, i.e., a “lit state” and an “unlit state” because it emits light through discharge. In other words, the discharge cell only represents two levels of luminance consisting of minimum luminance (unlit state) and maximum luminance (lit state).
A driver
100
performs gradation driving based on a subfield method for the PDP
10
comprising the discharge cells as display cells carrying pixels in order to realize a halftone luminance display corresponding an input video signal. The subfield method involves dividing one field display period into a plurality of subfields, and allocating each of the subfields with a number of times light emission is performed, corresponding to weighting applied to the respective subfields. For example, one field display period is divided into four subfields SF
1
-SF
4
, as shown in
FIG. 2
, which are allocates with the numbers of times of light emission as follows:
SF
1
: 1
SF
2
: 2
SF
3
: 4
SF
4
: 8
Here, the driver
100
converts an input video signal to 4-bit pixel data corresponding to each pixel. A first to a fourth bit of pixel data correspond to the subfields SF
1
-SF
4
, respectively. Then, the subfield method based gradation driving causes discharge cells to emit light the aforementioned numbers of times in the subfields corresponding to the respective bit digits in accordance with a logical level of each bit of the pixel data.
FIG. 3
illustrates a variety of driving pulses applied by the driver
100
to the column electrodes and row electrode pairs of the PDP
10
in each of the subfields for performing the light emission driving as described above, and timings at which the driving pulses are applied.
First, in a simultaneous reset stage Rc shown in
FIG. 3
, the driver
100
simultaneously applies the row electrodes X
1
-X
N
with a reset pulse RP
X
of positive polarity and the row electrodes Y
1
-Y
N
with a reset pulse RP
Y
of negative polarity. In response to these reset pulses RP
X
and RP
Y
, all discharge cells in the PDP
10
are discharged or reset to uniformly form a wall charge of a predetermined amount within the respective discharge cells. In this manner, all the discharge cells in the PDP
10
are once initialized to “light emitting cells.”
Next, in an addressing stage Wc, the driver
100
extracts one bit corresponding to this subfield from the 4-bit pixel data as described above, and generates a pixel data pulse having a pulse voltage corresponding to the logical level of the bit. For example, in the subfield SF
1
, the driver
100
generates a pixel data pulse having a pulse voltage corresponding to the logical level of a first bit of the pixel data. In this event, the driver
100
generates the pixel data pulse having a high voltage pulse when the logical level of the first bit is at “1” and a low voltage (zero volt) pulse when at “0.” Then, the driver
100
applies one display line of pixel data pulses sequentially to the column electrodes D
1
-D
m
. Specifically, as illustrated in
FIG. 3
, the driver
100
first applies the column electrodes D
1
-D
m
with a pixel data pulse group DP
1
comprised of m pixel data pulses corresponding to a first display line, and next applies the column electrodes D
1
-D
m
with a pixel data pulse group DP
2
comprised of m pixel data pulses corresponding to a second display line. Similarly, the driver
100
subsequently applies the column electrodes D
1
-D
m
sequentially with pixel data pulse groups DP
3
-DP
n
corresponding to a third to an n-th display line, respectively. The driver
100
further generates a scanning pulse SP of negative polarity in synchronism with the timing at which each pixel data pulse group DP is applied, and sequentially applies the scanning pulse SP to the row electrodes Y
1
-Y
N
, as illustrated in FIG.
3
. In this event, a discharge selectively occurs only in discharge cells at intersections of the display lines applied with the scanning pulse SP with the column electrodes applied with the pixel data pulse at the high voltage (selective erasure discharge), thereby extinguishing the wall charges which have remained in these discharge cells. In this manner, the discharge cells initialized to the “lit discharge cell state” in the simultaneous reset stage Rc transitions to the “unlit discharge cell state.” On the other hand, the selective erasure discharge is not generated in discharge cells which have been applied with the pixel data pulse at the low voltage simultaneously with the scanning pulse SP, so that these cells maintain the state initialized in the simultaneous reset stage Rc, i.e., “lit discharge cell state.”
In other words, the addressing stage Wc is executed to set each of the discharge cells in the PDP
10
either to the “lit discharge cell state” or to the “unlit discharge cell state” in accordance with the pixel data corresponding to the input video signal.
Next, in a light emission sustain stage Ic, the driver
100
alternately applies the row electrodes X
1
-X
n
and Y
1
-Y
n
with sustain pulses IP
X
and IP
Y
of positive polarity as illustrated in
FIG. 3
, the number of times allocated to each subfield as mentioned above. In this event, only those discharge cells in which the wall charges remain in the discharge space, i.e., those discharge cells which are in the “lit discharge cell state” discharge each time they are applied with the sustain pulses IP
X
and IP
Y
(sustain discharge). In other words, those discharge cells in which the selective erasure discharge was not generated in the addressing stage Wc repeat light emission associated with the sustain discharge the number of times allocated to each subfield as mentioned above to sustain the light emitting state.
Then, in the erasure stage E, the driver
100
applies the row electrodes Y
1
-Y
n
with an erasure pulse EP as illustrated in FIG.
3
. The application of the erasure pulse EP causes an erasure discharge to be generated in all the discharge cells of the PDP
10
, thereby extinguishing the wall charges remaining in the respective discharge cells.
The foregoing sequence of operations comprised of the simultaneous reset stage Rc, addressing stage Wc, light emission sustain stage Ic and erasure stage E is executed in each of the subfields SF
1
-SF
4
shown in FIG.
2
. According to the driving as described, light is emitted associated with the sustain discharge number of times corresponding to a luminance level of an input video signal through one field display period to provide visually perceived intermediate luminance in accordance with the number of times of light emission. According to the gradation driving based on the four subfields SF
1
-SF
4
as shown in
FIG. 2
, it is possible to represent 16 lev
Alemu Ephrem
Pioneer Corporation
Sughrue & Mion, PLLC
Wong Don
LandOfFree
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