Method of driving plasma display panel

Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix

Reexamination Certificate

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Details

C345S063000

Reexamination Certificate

active

06356249

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of driving a plasma display panel which is capable of improving the brightness in driving the plasma display panel in a sub-frame method.
2. Description of the Related Art
Recently, a plasma display panel(PDP) feasible to the fabrication of large-scale panel has been available for a flat panel display device. The PDP controls a discharge interval of each pixel to display a picture. Such a PDP typically includes a PDP of alternating current(AC) system having three electrodes and driven with an AC voltage as shown in FIG.
1
.
The PDP shown in
FIG. 1
includes a display panel
10
having 480×1920 discharge cells arranged in a matrix pattern, a controller
20
for converting an input video signal into a digital video data and for generating control signals, a first sustaining driver
14
for responding to a control of the controller
20
to drive first sustaining electrodes Y
1
to Y
480
, a second sustaining driver
16
for responding to a control of the controller
20
to drive second sustaining electrodes Z
1
to Z
480
, and an address driver
18
for responding to a control of the controller
20
to drive address electrodes A
1
to A
1920
. The display panel
10
has 480×1920 red(R), green(G) and blue(B) discharge cells
12
arranged in a matrix pattern to display a color picture of 480×640 resolution. To this end, the display panel
10
includes
480
first sustaining electrodes Y
1
to Y
480
arranged, in parallel, in the vertical direction, second sustaining electrodes Z
1
to Z
480
arranged alternately with the first sustaining electrodes Y
1
to Y
480
, and
1920
address electrodes X
1
to X
1920
arranged perpendicularly to the first and second sustaining electrodes Y
1
to Y
480
and Z
1
to Z
480
with having a discharge space therebetween. Discharge cells
12
are provided at each intersection between the first and second sustaining electrodes Y
1
to Y
480
and Z
1
to Z
480
and the address electrodes X
1
to X
1920
. Accordingly, in the discharge cell
12
, as shown in
FIG. 2
, the first and second sustaining electrodes Yi and Zi are formed, in parallel, on an upper substrate
22
, and the address electrodes Ai are formed on a lower substrate
28
. The first sustaining electrodes Yi and the address electrodes Ai allows an address discharge to be generated. The first and second sustaining electrodes Yi and Zi keep a discharge. A dielectric layer
24
and MgO protective film
26
is sequentially disposed on the upper substrate
22
formed with the first and second sustaining electrodes Yi and Zi. The dielectric layer
24
accumulates an electric charge during the discharge and limits a discharge current. The protective film
26
protects the dielectric layer
24
and the first and second sustaining electrodes Yi and Zi from a sputtering followed during the discharge. A fluorescent layer
30
generating R, G and B visible lights is coated on the lower substrate
28
formed with the address electrode Ai. The fluorescent layer
30
is usually coated to extend until the vicinity of the upper edge of a barrier rib(not shown). The barrier rib is formed in parallel to the address electrodes Ai between the upper substrate
22
and the lower substrate
28
. A discharge gas for emitting an ultraviolet(UV) is injected into the discharge space during the discharge. In the discharge cell with the structure as described above, an address discharge is caused by a voltage difference between a data signal applied to the address electrodes Ai and a scanning signal applied to the first sustaining electrodes Yi to generate a wall charge. The discharge is sustained by the wall charge and a sustaining pulse applied alternately to the first and second sustaining electrodes Yi and Zi. A fluorescent layer
30
is radiated by an ultraviolet generated at the time of this sustaining discharge to emit a visible light into the exterior.
In
FIG. 1
, the controller
20
digitizes an analog image signal VIDEO inputted from the exterior to convert it a digital video data, and separates and outputs the digital video data for each bit. Also, the controller
20
outputs the video data on a basis of a clock signal CLK, a horizontal synchronous signal HS and a vertical synchronous signal VS and generates various control signals. The first sustaining driver
12
responds to a control signal from the controller
20
to apply a scanning signal, etc. to the
480
first sustaining electrodes Y
1
to Y
480
. The second sustaining driver
14
responds to a control signal from the controller
20
to apply a discharge sustaining signal to the
480
second sustaining electrodes Z
1
to Z
480
commonly. The address driver
18
responds to a video data and a control signal from the controller
20
to apply a video data signal to the
1920
address electrodes A
1
to A
1920
.
Accordingly, the PDP allows the discharge cells
12
arranged in a matrix pattern to be selectively radiated in accordance with a video data signal to display a picture corresponding to the video data signal. In this case, the PDP employs a modulation technique in which a radiation frequency is proportional to a video signal to implement a gray level. Specifically, as shown in
FIG. 3
, one frame interval is divided into sub-field intervals corresponding to the bit number of the digitized video data. In each sub-field interval, a radiation having the frequency proportional to a weighting value of the video data is progressed to provide a gray scale display.
For instance, when a picture is displayed in 256 gray scales by making use of 8 bit video data, one frame display interval (e.g., {fraction (1/60)} sec=16.7 msec) in each discharge cell
12
is divided into 8 sub-field intervals SF
1
to SF
8
as shown in FIG.
3
. Each sub-field interval SF
1
to SF
8
is again divided into a reset interval RP, an address interval AP and a sustaining interval SP. A weighting value is given at a ratio of 1:2:4:8: . . . :128 in the sustaining interval SP. Herein, the reset interval RP is a time period for initializing the discharge cell, the address interval AP is a time period for causing a selective address discharge in accordance with a logical value of the video data, and the sustaining interval SP is a time period for allowing the discharge to be maintained at the discharge cell generating the address discharge. The reset interval RP and the address interval AP are equally assigned in each sub-field interval.
A driving technique of separating the reset, address and sustaining intervals every sub-field interval is called “sub-field driving method”. In such a sub-field method, a display sequence of the sub-field corresponding to each bit is made by a certain sequence of SF
1
, SF
2
, SF
3
, SF
4
, SF
5
, SF
6
, SF
7
and SF
8
as shown in FIG.
4
. In the address interval of each sub-field SF
1
to SF
8
, one bit data of 8 bit video data corresponding to each discharge cell is applied in a line sequence to cause a selective address discharge. Specifically, least significant bit data are applied in the address interval of the first sub-field SF
1
, next least significant bit data are applied in the address interval of the second sub-field SF
2
, and most significant bit data are applied in the address interval of the eighth sub-field SF
8
. In the sustaining interval of each sub-field SF
1
to SF
8
, the discharge is maintained only at the discharge cell generating the address discharge. In this case, in the sustaining interval SP of each sub-field SF
1
to SF
8
, a weighting value is given at a ratio of 1:2:4:8: . . . :128 and a gray scale display corresponding to the weighting value is carried out. Gray scales displayed at each sub-field in one frame interval are combined to implement one gray scale in 256 levels.
However, the above-mentioned sub-field driving method has a problem in that the brightness and the luminous efficiency are low. More specifically, assuming that one frame interval is {fraction (1/60)} second, that is, 16.67 ms a

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