Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-09-13
2002-01-01
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S068000, C315S169400
Reexamination Certificate
active
06335712
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a driving method for a plasma display panel, and more particularly to a plasma display panel driving method that is adaptive for a high speed drive and is capable of improving the contrast.
2. Description of the Related Art
Recently, a plasma display panel(PDP) feasible to the fabrication of large-scale panel has been available for a flat panel display device. The PDP controls a discharge interval of each pixel to display a picture. As shown in
FIG. 1
, such a PDP typically includes a PDP of alternating current (AC) system having three electrodes and driven with an AC voltage.
FIG. 1
shows the conventional AC system PDP having discharge cells arranged in a matrix pattern. Each pixel of the AC system PDP includes an upper plate having a scanning electrode
12
A, a sustaining electrode
12
B, an upper dielectric layer
14
and a protective film
16
disposed on the upper substrate
10
, and a lower plate having an address electrode
20
, a lower dielectric layer
22
, a barrier rib
24
and a fluorescent layer
26
disposed on a lower substrate
18
. The upper substrate
10
and the lower substrate
18
are spaced, in parallel, by the barrier rib
24
. The scanning electrode
12
A and the sustaining electrode
12
B are formed, in parallel, on the upper substrate
10
. Wall charges produced during the plasma discharge are accumulated on the upper dielectric layer
14
and the lower dielectric layer
22
. The protective film
16
prevents a damage of the upper dielectric layer
14
due to the sputtering, thereby prolonging a life of PDP as well as improving an emissive efficiency of secondary electrons. Usually, MgO is used as the protective film
16
. The address electrode
20
is crossed with the scanning electrode
12
A an d the sustaining electrode
12
n. A data signal is applied to the address electrode
20
. The barrier rib
24
is formed in parallel to the address electrode
20
. The barrier
24
prevents an ultraviolet ray and a visible light produced by the discharge from being leaked into the adjacent cells. The fluorescent layer
26
is coated on the surfaces of the lower dielectric layer
22
and the barrier rib
24
to generate any one of red, green and blue visible lights. An inactive gas for a gas discharge is injected into a discharge space between the upper or lower plate and the barrier rib.
Referring to
FIG. 2
, a driving apparatus for the AC system PDP) includes a PDP
30
arranged in a matrix pattern in such a manner that mxn pixel cells are connected to scanning electrode lines Y
1
to Ym, sustaining electrode lines Z
1
to Zm and address electrode lines X
1
to Xn, a scanning electrode driver
32
for driving the scanning electrode lines Y
1
to Ym, a sustaining electrode driver
34
for driving the sustaining electrode lines Z
1
to Zm, and first and second address electrode drivers
36
A and
36
B for divisionally driving odd-numbered address electrode lines X
1
, X
3
, . . . , Xn−3, Xn−1 and even-numbered address electrode lines X
2
, X
4
, . . . , Xn−2, Xn. The scanning electrode driver
32
applies a scanning pulse and a sustaining pulse to the scanning electrode lines Y
1
to Ym sequentially, thereby allowing the pixel cells
1
to be sequentially scanned in a line unit and allowing a discharge at each of the mxn pixel cells to be sustained. The sustaining electrode driver
34
applies a sustaining pulse to all the sustaining electrode lines Z
1
to Zn. The first and second address electrode drivers
36
A and
36
B supply an image data to the address electrode lines X
1
to Xn in such a manner to be synchronized with the scanning pulse. The first address electrode driver
36
A supplies an image data to the odd-numbered address electrode lines X
1
, X
3
, . . . , Xn−3, Xn−1 while the second address electrode driver
36
B supplies an image data to the even-numbered address electrodes X
2
, X
4
, . . . , Xn−2, Xn.
Such an AC system PDP implements the gray level by controlling a light quantity depending on a discharge time. in other words, the AC system PDP controls a discharge time to make the contrast and the chrominance of a picture different. To this end, the AC system PDP mainly uses a driving system such as an addressing display separated (ADS) system. The ADS system divides one frame into a number of sub-fields, each of which is divided into an address interval and a sustaining interval different from each other, in accordance with a gray level to be implemented. For instance, when it is intended to display a picture with 256 gray levels, a frame interval corresponding to 1/60 second is divided into 8 sub-fields SF1 to SF8. Further, each of the 8 sub-fields SF1 to SF8 is again divided into an address interval and a sustaining interval.
FIG. 3
shows drive waveforms of the AC system PDP. In
FIG. 3
, a writing pulse WP is applied to the address electrode line X in an address interval, whereas a scanning pulse—SCP and a sustaining pulse SUSP are applied to the scanning electrode line Y in an address interval and in a sustaining interval, respectively. Also, the sustaining pulse SUSP is applied to the sustaining electrode line Z in a sustaining interval. In the address interval, an address discharge is generated between the address electrode line X and the scanning electrode line Y at a time t1 when the writing pulse WP begins to be applied. At this time, a desired level of direct current voltage is applied to the sustaining electrode lines Z. This direct current voltage permits an address discharge between the address electrode line X and the scanning electrode line Y to be generated stabbly. By the address discharge, wall charges are accumulated on the dielectric layer
14
within the discharge space at a time t2. The writing pulse WP has a pulse width more than about 3 &mgr;s to sustain the discharge during a time allowing a formation of the wall charges. Subsequently, a sustaining interval begins at a time t3. At the time t3, a sustaining discharge is generated between the scanning electrode line Y and the sustaining electrode line Z from the sustaining pulse SUSP applied to the scanning electrode line Y. At a time t4 when the sustaining pulse SUSP remains at a high level, wall charges are accumulated on the dielectric layer
14
. The wall charges make a memory effect allowing an electric field within the discharge space to be sustained. In other words, the sustaining discharge is generated from an electric field formed by the wall charges and an electric field formed by the sustaining pulse SUSP. Accordingly, any discharge is not generated within the pixel cell
1
in which wall charges are not formed even when the sustaining pulse SUSP is applied. At a time when the sustaining pulse SUSP applied to the scanning electrode line Y changes into a low level and, at the same time, the sustaining pulse SUSP begins to be applied to the sustaining electrode line Z, a sustaining discharge is again generated between the scanning electrode line Y and the sustaining electrode line Z. At a time t6, wall charges are formed As described above, the sustaining discharge and the formation of wall charges are continuously provided by the sustaining pulse SUSP applied to the scanning electrode line Y and the sustaining electrode line Z alternately to thereby sustain a discharge of the pixel cells
1
selected by the address discharge. After the sustaining interval, an erasing pulse EP is applied to the scanning electrode line Y between t7 and t8 within an erasing interval. A voltage level of the erasing pulse EP is set to have a lower value than that of the sustaining pulse SUSP, and a pulse width thereof is set to have a narrower value (i.e., about 1 &mgr;s) than that of the sustaining pulse SUSP. By this erasing pulse EP, a discharge is generated between the scanning electrode line Y and the sustaining electrode line Z. Since a pulse width of the erasing pulse is set to be shorter than a time allowing a formation of the wall charges, a discharge d
Fleshner & Kim LLP
LG Electronics Inc.
Liang Regina
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