Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-05-28
2001-08-07
Nguyen, Chanh (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S094000
Reexamination Certificate
active
06271817
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving a liquid crystal display device and, in particular, to a method of driving an active-matrix liquid crystal display device utilizing a two-terminal element as a switching element of a pixel.
2. Related Art
An active-matrix type of liquid crystal display device provides a higher contrast than a conventional passive type of device, so they are becoming increasingly common in various manufacturing fields that use displays. Two types of active elements are used: two-terminal type and three-electrode type. The two-terminal type is considered to be superior from the economical point of view.
Some of the two-terminal type of active elements that are used are metal-insulator-metal (MIM) elements, ring diodes, and varistors.
In general, a two-terminal type of active element utilized in an active-matrix type of liquid crystal display device has the I-V characteristic shown in FIG.
3
. In other words, it uses a switching function caused by a non-linear characteristic of current with respect to applied voltage, to charge and discharge an effective electrical charge applied to the picture element.
The configuration of an active-matrix liquid crystal display device using a two-terminal type of active element is shown in FIG.
1
. In this figure, reference number
101
denotes a column drive circuit (X driver) that drives column electrodes of a liquid crystal panel
115
, and
102
denotes a row drive circuit (Y driver) that drives row electrodes thereof.
In the X driver
101
, reference number
104
denotes an AC video generation circuit which accepts a video signal (P) input, and generates an AC video signal in synchronization with an AC inversion signal FRX. Reference number
103
denotes a shift register that is activated by a shift start signal DX, performs a shift operation in synchronism with a shift clock signal XSCL, and sequentially generates a sampling signal Sm. Reference number
105
denotes a first analog switch that samples the AC video signal generated from the AC video generation circuit
104
by the sampling signal Sm and holds it in a capacitor
106
. The capacitor
106
is a first sample-and-hold capacitor. Reference number
107
denotes a second analog switch that transfers the sampled video signal held in the capacitor
106
to another capacitor
108
by a latch pulse LP. The capacitor
108
is a second sample-and-hold capacitor. Reference number
109
denotes a buffer amplifier that drives a column electrode Xm on the basis of the video signal held in the capacitor
108
.
Within the Y driver
102
, reference number
110
denotes an inverter that uses Vp and −Vp as power sources and generates a selection voltage signal Vs in synchronization with an AC inversion signal FRY. Reference number
111
denotes a shift register that is activated by a shift start signal DY, performs a shift operation in synchronism with a shift clock signal YSCL, and generates a selection signal Cn. Reference number
112
denotes a power source selection switch for one cell of a drive circuit for a row electrode Yn.
The internal configuration of the selection switch
112
is shown in FIG.
2
. The AC inversion signal FRY and selection signal Cn are input to shift register latches which consists of NOR gates
201
and
202
. An output from the NOR gate
201
and an inverted signal obtained by an inverter
203
from the selection signal Cn are both input to AND gates
204
and
205
, and outputs therefrom are input to gate electrodes of analog switches
207
and
208
, respectively. The selection signal Cn is also input to a gate electrode of an analog switch
206
. The selection voltage signal Vs and power sources −Va and Va are input to source electrodes of the analog switches
206
to
208
, respectively, drain electrodes of the analog switches
206
to
208
are connected in common, and a signal Yn (a signal for driving the row electrode Yn) is output therefrom.
Reference number
115
denotes a liquid crystal panel. Column electrodes Xm and row electrodes Yn are formed on the respective substrates of the liquid crystal panel
115
, and at each intersection thereof a non-linear element
114
and a liquid crystal layer
113
are arranged in series to form a pixel. In this case, voltages applied to the liquid crystal layer
113
and the non-linear element
114
are Vm and Vl, with respect to the row electrode.
The non-linear element
114
has the current-voltage characteristic shown in FIG.
3
. As can be seen from this figure, when the applied voltage is small, the current is extremely small; when the applied voltage is large, the current characteristic increases steeply.
The operation of the example of a prior art liquid crystal display device shown in FIG.
1
and
FIG. 2
will now be described with reference to the timing charts of
FIG. 4
to FIG.
6
.
As shown in
FIG. 4
, the video signal (P) is inverted in synchronization with the AC inversion signal FRX (when FRX=1, the phase of (P) is positive; when FRX=0, the phase of (P) is negative) to obtain an AC video signal
104
. In this case, Va is the 100% white level of the positive-phase video signal and the 0% white level (pedestal level) of the negative-phase video signal, and −Va is the 0% white level (pedestal level) of the positive-phase video signal and the 100% white level of the negative-phase video signal. The shift start signal DY of the Y driver is sequentially transferred by the shift clock signal YSCL to generate selection signals C
1
, C
2
, C
3
. . . Cn, . . . The latch pulse LP and the shift start signal DX of the X driver are input every horizontal scanning period.
An enlarged view of a specific horizontal scanning period is shown at the bottom of FIG.
4
. The latch pulse LP is positioned roughly at the synchronization portion of the video signal, and it transfers the video signal that was sampled and held in the capacitor
106
during the previous horizontal scanning period to the capacitor
108
. The shift start signal DX is positioned roughly at the start of the video signal portion in one horizontal scanning period, and it is transferred by the shift clock signal XSCL to generate sampling signals S
1
, S
2
, S
3
. . . Sm, . . . For example, the nth video signal
104
sampled by sampling signal Sm (the sampling position marked by a circle (∘) in the
FIG. 4
) is output to the column electrode Xm at the timing of the (n+1)th video signal after one horizontal scanning period.
FIG. 5
is a timing chart of the components shown in FIG.
2
. According to logic combination of the selection signal Cn and the AC inversion signal FRY (in this prior art example, a common AC inversion signal is input to both the X driver and the Y driver—in other words, FRX=FRY), the outputs of the shift register latches
201
and
202
are made to repeatedly invert between 1 (Cn=1, FRY=0) and 0 (Cn=1, FRY=1). When Cn=1, Yn outputs the selection voltage signal Vs (which is at −Vp when FRY=1 or Vp when FRY=0); when Cn=0 (called the non-selection period or hold period), Yn outputs a voltage corresponding to the polarity at the immediately previous selection (when Cn=1)—i.e., it is Va after a positive (Vp) selection or −Va after a negative (−Vp) selection.
FIG. 6
is a timing chart of the column electrode signal Xm and the row electrode signal Yn, together with a difference signal Xm−Yn thereof. Video data which corresponds to the mth column in the horizontal direction along the liquid crystal panel
115
is sequentially sampled by the AC video signal, and is output as the line electrode signal Xm. The row electrode signal Yn outputs the selection voltage signal Vs during a selection period Ts, and a non-selection potential Va or −Va during a non-selection period Th. The non-selection potential after a selection at positive potential Vp is Va, and that after a selection at negative potential −Vp i
Konishi Masanori
Matsueda Yojiro
Mikoshiba Hiroaki
Niwa Kenji
Wakai Yoichi
Nguyen Chanh
Oliff & Berridg,e PLC
Seiko Epson Corporation
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