Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2003-03-11
2004-06-01
Vu, David (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169400, C345S063000, C345S068000
Reexamination Certificate
active
06744218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving method of plasma display panels, and more particularly, to a plasma display panel driving method in which a reset step, an address step, and a display sustaining step are performed on unit subfields.
2. Background Description
FIG. 1
shows the structure of a general 3-electrode surface-discharge type plasma display panel
1
.
FIG. 2
shows a display cell of the plasma display panel
1
of FIG.
1
. Referring to
FIGS. 1 and 2
, address electrode lines A
R1
, A
G1
through A
Gm
, and A
Bm
(not shown are the ranges A
R1
-A
Rm
and A
B1
through A
Bm
), front dielectric layer
11
and rear dielectric layer
15
, Y electrode lines Y
1
through Y
n
, X electrode lines X
1
, through X
n
, a fluorescent layer
16
, barrier ribs
17
, and a magnesium monoxide (MgO) layer
12
as a protective membrane are provided between front glass substrate
10
and rear glass substrates
13
of the general surface-discharge type plasma display panel
1
.
The address electrode lines A
R1
, A
G1
through A
Gm
, and A
Bm
are disposed on the front surface of the rear glass substrate
13
in a predetermined pattern, and entirely coated with the rear dielectric layer
15
. The barrier ribs
17
are formed parallel to the address electrode lines A
R1
, A
G1
through A
Gm
, and A
Bm
on the front surface of the rear dielectric layer
15
. The barrier ribs
17
define a discharge area on each display cell and prevents an optical cross-talk between display cells. The fluorescent layer
16
is formed between the barrier ribs
17
.
The X electrode lines X
1
, through X
n
and the Y electrode lines Y
1
through Y
n
are formed on the rear surface of the front glass substrate
10
in a predetermined pattern so that they intersect the address electrode lines A
R1
, A
G1
through A
Gm
, and A
Bm
at right angles. Each intersection corresponds to a display cell. To form each of the X electrode lines X
1
through X
n
, a transparent conductive electrode line X
na
of
FIG. 2
, such as an indium tin oxide (ITO), is combined with a metallic electrode line X
nb
of
FIG. 2
for increasing conductivity. Likewise, to form each of the Y electrode lines Y
1
through Y
n
, a transparent conductive electrode line Y
na
of
FIG. 2
, such as an indium tin oxide (ITO) is combined with a metallic electrode line Y
nb
of
FIG. 2
for increasing conductivity. The X electrode lines X
1
through X
n
and the Y electrode lines Y
1
through Y
n
are entirely coated with the front dielectric layer
11
. The magnesium monoxide (MgO) layer
12
, for protecting the panel
1
from a strong electric field, is formed on the entire rear surface of the front dielectric layer
11
. Plasma forming gas fills a discharge space
14
.
The plasma display panel is driven by sequentially performing a reset step, an address step, and a display sustaining step on unit subfields. In the reset step, the charge states on display cells to be driven are made uniform. In the address step, the charge state of display cells to be turned on is set, and the charge state of display cells to be turned off is also set. In the display sustaining step, the display cells to be turned on perform display discharging.
Here, multiple unit sub-fields operating based on the above-described driving principle are included in a unit frame, so a desired gray scale can be displayed by the display sustaining periods of the respective subfields.
FIG. 3
shows a conventional address-display separation driving method of the Y electrode lines of the plasma display panel of FIG.
1
. Referring to
FIG. 3
, a unit frame is divided into 8 sub-fields SF
1
through SF
8
in order to achieve time-division gray scale display. Each of the sub-fields SF
1
through SF
8
is divided into an address period A
1
through A
8
and a display sustain period S
1
through S
8
.
In each of the address periods A
1
through A
8
, while a display data signal is applied to the address electrode lines A
R1
, A
G1
through A
Gm
, and A
Bm
of
FIG. 1
, appropriate scanning pulses are sequentially applied to the Y electrode lines Y
1
through Y
n
. During the application of the scanning pulses, if a high-level display data signal is applied to an address electrode line, wall charges are formed on a discharge cell corresponding to the address electrode line, but the other discharge cells do not gain wall charges.
In each of the display sustain periods S
1
through S
8
, a display discharge pulse is applied to all of the X electrode lines X
1
through X
n
and all of the Y electrode lines Y
1
through Y
n
in such a way that the display discharge pulse alternates between them. Thus, display discharge occurs on discharge cells having wall charges formed in each of the address periods A
1
through A
6
. Accordingly, the luminance of a plasma display panel is proportional to the length of the display sustain periods S
1
through S
8
for a unit frame. In the plasma display panel of
FIG. 3
, the length of the display sustain periods S
1
through S
8
for a unit frame is 255T (T denotes a unit time). Hence, a unit frame can express 256 gray scales including a zero gray scale, where no display discharge occurs.
A time 1T, corresponding to 2
0
, is set for the display sustain period S
1
of the first sub-field SF
1
. A time 2T, corresponding to 2
1
, is set for the display sustain period S
1
of the second sub-field SF
2
. A time 4T, corresponding to 2
2
, is set for the display sustain period S
3
of the third sub-field SF
3
. A time 8T, corresponding to 2
3
, is set for the display sustain period S
4
of the fourth sub-field SF
4
. A time 16T, corresponding to 2
4
, is set for the display sustain period S
5
of the fifth sub-field SF
5
. A time 32T, corresponding to 2
5
, is set for the display sustain period S
6
of the sixth sub-field SF
6
. A time 64T, corresponding to 2
6
, is set for the display sustain period S
7
of the seventh sub-field SF
7
. A time 128T, corresponding to 2
7
, is set for the display sustain period S
8
of the eighth sub-field SF
8
.
Accordingly, it can be seen from
FIG. 3
that when sub-fields to be displayed are appropriately selected from the 8 sub-fields, any of the selected sub-fields can display 256 gray scales including a zero gray scale, in which display discharge does not occur.
In the above-described address-display separation driving method, since the subfields SF
1
through SF
8
are temporally separated in a unit frame, the address period and the display sustain period are temporally separated in each of the subfields SF
1
through SF
8
. More specifically, in an address period, each pair of X and Y electrodes is addressed, and waits for the next operation until the other pairs of X and Y electrodes are all addressed. Consequently, the time for the address period in each subfield is lengthened, while the display sustain period is relatively shortened. This lowers the luminance of light emitted from a plasma display panel adopting the above method. In order to solve this problem, an address-while-display driving method as shown in
FIG. 4
have been developed.
FIG. 4
shows a conventional address-while-display driving method of the Y electrode lines of the plasma display panel of FIG.
1
. Referring to
FIG. 4
, a unit frame is divided into 8 subfields SF
1
through SF
8
in order to achieve time-division gray-scale display. Here, the subfields overlap with one another with respect to the Y electrode lines Y
1
through Y
n
to constitute a unit frame. Hence, all of the subfields SF
1
through SF
8
exist at every time point and an addressing time slot is set between display discharge pulses in order to perform each addressing.
A reset step, an address step, and a display sustaining step are performed on each of the subfields, and the time allocated to each of the subfields is determined based on a display discharging time corresponding to a gray scale. If 8-bit image data displays 256 gray scales per unit frame and the unit frame (generally, 1/60 sec) is divided into 255 unit peri
Chae Seung-Hun
Kang Kyoung-Ho
McGuire Woods LLP
Samsung SDI & Co., Ltd.
Vu David
LandOfFree
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