Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2001-07-31
2004-06-29
Huson, Gregory L. (Department: 3751)
Metal working
Method of mechanical manufacture
Electrical device making
C216S065000
Reexamination Certificate
active
06754951
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of drilling a circuit substrate. More specifically, the present invention relates to a method of ablating an IC circuit substrate by laser.
2. Description of the related art
A laminated board is the substrate often used as a printed circuit board and an IC package substrate in current electronic-related industries. With the demand for increased integration of electronic products, the electronic products are designed to be smaller in size, lighter in weight and to have high performance. Accordingly, it is necessary to obtain a laminated board having an increased density, a decreased thickness, a reduced pitch between circuits and a smaller through hole.
FIGS. 1A
to
1
C are schematic, cross-sectional views of a conventional process of fabricating a circuit substrate are shown.
As shown in
FIG. 1A
, an inner substrate
104
having two circuit layers
102
is shown. The circuit layer
102
can be formed on both surfaces of an insulating layer
100
by photolithography and etching process.
As shown in
FIG. 1B
, an oxidation is carried out on the inner circuit layer
102
to form oxides thereon. That is, the surfaces of the inner circuit layer
102
are oxidized to make the surface thereof coarser, so that the adhesion of the inner circuit layer
102
to an insulator(s) is enhanced. Each side of the inner substrate
104
is provided with an adhesive
106
and a copper foil
108
. Then, laminating is carried out for formation of another circuit layer in the subsequent step. It is noted that the adhesive
106
and the inner circuit layer
102
are bonded and cured before formation of another circuit layer in the subsequent step. However, the adhesive
106
and the inner circuit layer
102
are bonded only by pressing the adhesive
106
toward the inner circuit layer
102
with heating, which is known as thermal pressing, and by cooling while pressing, which is known as cool pressing.
As shown in
FIG. 1C
, a through hole or a guide hole
120
, which is used for connection or installation, is formed at the position where a component is to be installed, and layers are communicated with each other, which is a step called drilling. After drilling, the insulating layer
100
becomes an insulating layer
110
. After drilling, the inner circuit layer
102
becomes an inner circuit layer
112
. After drilling, the copper foil
108
becomes copper foil
118
. A plating through hole (PTH) is formed by plating the via
120
with copper to form a copper foil
122
in the via
120
. The copper foils
118
and
122
are etched by using a mask to form an outer circuit layer. In the case of a four-layered laminate, a solder mask is applied on the outer circuit layer to expose the portions where other components are connected. Finally, a solder layer is formed on portions exposed from the solder mask on the outer circuit layer so as to protect the copper surface from being oxidized and increase the adhesion to the solder layer when soldering. Therefore, the portions having a solder mask applied will not be contaminated with the solder, and a short circuit can be thus avoided.
The formation of the via
120
can be achieved by drilling using drilling gimlets. However, the use of drilling gimlets has some disadvantages such as poor availability, high price, easily breakable, and difficulty in controlling the depth of the via. Drilling using punches always generates burrs. In the case of ablating using a CO
2
laser, the depth of ablating is limited due to the lower energy of the CO
2
laser. In the case of UV YAG laser ablating, the ablating speed is limited since a small beam size for the laser is used in the UV YAG laser ablating. In general, a positioning hole is first defined in the outer copper layer by photolithography and etching to expose part of the insulating layer. Then, the insulating layer exposed by the positioning hole is ablated through laser until the insulating layer is penetrated. If photolithography and etching are used in combination with laser ablating, then some disadvantages are generated, such as a complicated process, inconstant precision of forming a via, higher cost, and the difficult formation of a micro-via with a size that is less than 4 mil.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide a method of ablating a circuit substrate to resolve problems such as limited speed of YAG laser ablating and to increase the alignment of the inner layer in a built-up process.
It is another object of the present invention to provide a method of ablating a circuit substrate. The process comprises at least providing a circuit substrate that at least includes a core layer and a metal layer covering one or both surfaces of the core layer. A half-etching process is carried out to etch the metal layer on the circuit substrate with an etchant to partly reduce the thickness of the metal layer. Then, the metal layer is subject to a surface treatment in order to increase the absorption of the laser. A via is formed in the circuit substrate by laser ablating.
According to one preferred example of the present invention, the core layer is formed by alternately superposing a plurality of insulating layers and a plurality of patterned circuit layers. In the method of drilling a circuit substrate according to the present invention, CO
2
laser ablating with high energy is used and the copper foil is subject to a surface treatment to increase the absorption of the laser. Accordingly, disadvantages in the prior art, such as limited depth in a conventional CO
2
laser ablating and limited speed in the conventional YAG laser ablating, can be prevented. Since the copper foil and the insulating layer are ablated directly in the method of the present invention, the process can be thus simplified. Meanwhile, the precision of forming a via is not affected by the expansion/contraction and exposure of the metal layers, thereby improving the alignment.
REFERENCES:
patent: 6240636 (2001-06-01), Asai et al.
patent: 6413868 (2002-07-01), Bartush et al.
Ho Sheng-Chun
Hsiao Min-Liang
Advanced Semiconductor Engineering Material, Inc.
deVore Peter
Huson Gregory L.
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