Method of doping a JFET region in a MOS-gated semiconductor devi

Details Method of doping a JFET region in a MOS-gated semiconductor devi Method of doping a JFET region in a MOS-gated semiconductor devi

1994-05-19

1995-06-06

Fourson, George

Fishing, trapping, and vermin destroying

437144, 437953, H01L 21265

Patent

active

054222885

ABSTRACT:
A MOS-gated semiconductor device may be manufactured by a process in which the neck region of the device is doped through a previously deposited polysilicon gate. In the method of the present invention, the dopant in the neck region of the device is not subjected to the same temperature history as the body dopant, thereby providing means to increase the ruggedness of the device and providing means by which the threshold voltage of the device may be controlled.

REFERENCES:
patent: 4376286 (1983-03-01), Lidow et al.
patent: 4810665 (1989-03-01), Chang et al.
patent: 5016066 (1991-05-01), Takahashi
patent: 5028552 (1991-07-01), Ushiku
patent: 5055895 (1991-10-01), Akiyama et al.
patent: 5248627 (1993-09-01), Williams

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