Method of digital logic simulation

Details Method of digital logic simulation Method of digital logic simulation

1980-05-13

1982-07-27

Smith, Jerry

Boots, shoes, and leggings

371 23, G06F 1520

Patent

active

043420931

ABSTRACT:
A logic simulation is executed using a real circuit as a part of a simulation model of a logic circuit subjected to the logic simulation. The simulation model is formed of the real circuit and a simulation circuit, and the operation of the real circuit and the logic simulation of the simulation circuit are performed alternately. The operation of the real circuit is performed in response to an input signal thereto representing the condition of the output node of the simulation circuit, while the logic simulation of the simulation circuit is executed in response to a stimulus in the form of an output signal of the real circuit which is applied to the input node of the simulation circuit.

REFERENCES:
patent: 3927371 (1975-12-01), Pomeranz et al.
E. G. Ulrich, "Exclusive Simulation of Activity in Digital Networks", Communications of the ACM, vol. 12, No. 2, Feb. 1969, pp. 102-110.
J. R. Armstrong et al., "Chip-Level Simulation of Microprocessors", Computer, vol. 13, No. 1, Jan. 1980, pp. 94-100.
S. A. Szygenda et al., "Digital Logic Simulation in a Time-Based, Table-Driven Environment Part 1. Design Verification", Computer, vol. 8, No. 3, Mar. 1975, pp. 24-36.

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