Fishing – trapping – and vermin destroying
Patent
1992-04-01
1997-03-25
Fourson, George
Fishing, trapping, and vermin destroying
437227, H01L 21301
Patent
active
056144458
ABSTRACT:
A process for manufacturing a semiconductor device is described comprising the steps of providing window openings in a photoresist mask layer for forming trench grooves on the surface of a p.sup.+ -type epitaxial silicon wafer where an integrated circuit is subsequently formed; providing window openings in the photoresist mask layer for forming dummy etched grooves in a scribe line zone on the wafer; and performing dry etching to remove material exposed by the window openings. The sum of the areas to be etched by dry etching accounts for not less than 5% of the total surface area on one side of the p.sup.+ -type silicon wafer. Trench grooves are formed in the integrated circuit region of the wafer and dummy etched grooves are formed in a scribe line zone of the wafer. Both the trench grooves and the dummy etched grooves are filled with polycrystalline silicon to provide a smooth wafer surface. The wafer is then cleaved along the scribe line zone. Accordingly, a high density of circuit elements can be realized by forming microminiature etching sections in a stable configuration while preventing side etching during the dry etching processing step. The semiconductor device resulting from the disclosed process is also described.
REFERENCES:
patent: 4916087 (1990-04-01), Tateoka et al.
patent: 4922318 (1990-05-01), Thomas et al.
patent: 5023188 (1991-06-01), Tanaka
Gottscho, R. et al, "Microscopic Uniformity in Plasma Etching", J. Vac. & Tech. (B) 10(5), Sep. 10, 1992, pp. 2133-2147.
Fourson George
Fuji Electric & Co., Ltd.
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