Method of determining settling time of a device under test

Details Method of determining settling time of a device under test Method of determining settling time of a device under test

1991-10-18

1992-11-10

Wieder, Kenneth A.

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Parameter related to the reproduction or fidelity of a...

324617, 324606, 341120, 307517, G01R 1912, G01R 2902

Patent

active

051627442

ABSTRACT:
Settling time of an electrical device under test in response to a step wave input voltage is determined by first establishing first and second output voltage levels which differ from a settled output voltage level by preestablished voltage differentials, and then determining the time after applying a step wave voltage to the device under test when the output voltage equals the first and second voltages. A voltage controlled oscillator is utilized in triggering the step wave voltage generator and in enabling a voltage comparator whereby the period of the voltage control oscillator is a measure of the settling time of the device under test.

REFERENCES:
patent: 3668522 (1972-06-01), Ghafghaichi
patent: 4364045 (1982-12-01), Spiegel
patent: 4795963 (1989-01-01), Ueno
Sheingold: "Analog-Digital Conversion Handbook"-Analog Devices-Norwood-Mass.-1972 edition-pp. II-116 to 127.

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