Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-03-18
2004-05-25
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06741093
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to measuring electrical properties of a product semiconductor wafer.
2. Description of Related Art
The performance of a MOS transistor is dependent on its threshold voltage (V
T
). Device V
T
is highly sensitive to both device geometry and processing. However, processing related parameters have a stronger impact on device V
T
and will continue to dominate for all sub-micron technologies. Therefore, highly sensitive and repeatable process measurements are and will continue to be essential in controlling device V
T
.
Among the various process related parameters, V
T
is most sensitive to carrier density profile in the channel region of a MOS transistor. Ion implantation into the channel region is used to produce the channel profile since it allows precise adjustment of V
T
.
In today's semiconductor wafers, the gate equivalent oxide thickness has decreased to as low as 15 angstroms. Hence, a higher channel doping level is required in order to maintain V
T
at an appropriate level and to control off-state leakage and to improve gate control of the channel charge. This makes tight control of V
T
more critical and, hence, more difficult.
Currently, monitor wafers are used to measure V
T
whereupon the measured value of V
T
can be utilized to adjust the ion implant of the channel regions of a product wafer. However, since the ion implant of channels and, hence, the resultant V
T
of these channels can vary from semiconductor wafer to semiconductor wafer, it is becoming increasingly necessary to measure V
T
on product wafers. In order to measure V
T
on product wafers, the measuring means must be non-contaminating, non-damaging, fast, and capable of measuring V
T
in product wafer scribe lines or test volumes. However, no means presently exist for measuring V
T
and, more particularly, ion implant in a product semiconductor wafer or variances in ion implants between two or more product wafers that meets all of these criteria.
It is, therefore, an object of the present invention to overcome the above problems and others by providing a method for measuring the ion implant of a semiconductor wafer. It is an object of the present invention to provide a method of determining variances in ion implant between two or more semiconductor wafers. Still other objects will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.
SUMMARY OF THE INVENTION
Accordingly, we have invented a method of determining one or more properties of a semiconductor wafer having a dielectric layer overlaying at least a portion thereof. The method includes providing a semiconductor wafer having a pattern of integrated circuits formed thereon and scribe lines separating the integrated circuits from one another. A probe is provided having an elastically deformable, electrically conductive tip. The probe tip is caused to contact a dielectric layer overlaying at least a portion of one of the scribe lines of the semiconductor wafer thereby forming a metal-oxide-semiconductor (MOS) structure. The probe tip has a contact area that is received within said scribe line when the probe tip contacts the dielectric layer. A capacitance-voltage (CV), current-voltage (IV), conductance-voltage (GV) or capacitance-time (Ct) type electrical stimulus is applied to the MOS structure. A response of the MOS structure to the electrical stimulus is measured and from the response at least one property of the dielectric layer, the semiconductor wafer and/or the interface therebetween is determined. The probe contacts the dielectric layer with a force whereby the probe tip elastically deforms within its elastic limits.
The semiconducting material comprising the semiconductor wafer can include an ion implanted dopant received in a test volume underlying the dielectric layer contacted by the probe tip.
When a CV type electrical stimulus is applied, the step of applying the stimulus includes the steps of superimposing an AC voltage on a DC voltage and sweeping the DC voltage between a first, starting voltage and a second, ending voltage. The step of measuring the response includes the step of acquiring capacitance values during the sweep of the DC voltage. The determining step includes the step of determining a dopant concentration in at least one layer of the test volume as a function of the acquired capacitance values and the voltage at which each capacitance value is acquired. A dopant implant dose can be determined in the test volume as a function of the dopant concentration in a plurality of layers of the test volume. The plurality of layers extend from adjacent the surface of the test volume in a direction into the test volume away from the surface.
The method can further include determining from the acquired capacitance values a minimum capacitance value (C
min
) of the test volume. The value for C
min
occurs when the test volume is depleted of majority carriers and a net recombination of majority carriers and minority carriers in or adjacent the test volume is at equilibrium. From the value for C
min
, a maximum space-charge depth of the test volume is determined. The maximum space-charge depth is a distance from the surface of the test volume where the depleted majority carriers reside when the test volume is at equilibrium. An average doping concentration in the test volume can then be determined from the maximum space-charge depth. A threshold voltage value V
T
can also be determined from the acquired capacitance values.
Comparisons of average doping concentrations of a reference semiconductor wafer and one or more semiconductor wafers under test can be utilized to determine if an ion implant process for the semiconductor wafers under test is varying outside of an acceptable tolerance.
We have also invented a method of determining one or more properties of a semiconductor wafer that includes providing a semiconductor wafer having a pattern of integrated circuits formed thereon and scribe lines separating the integrating circuits from one another. A probe is provided having an elastically deformable, electrically conductive tip. The probe tip is caused to contact at least a portion of one of the scribe lines of the semiconductor wafer. The probe tip has a contact area that is received within the scribe line. An electrical stimulus is applied between the probe tip and the semiconductor wafer and the response of the semiconductor wafer to the electrical stimulus is measured. From the response, at least one property of the semiconductor wafer is determined.
The probe tip can contact the semiconducting material comprising the semiconductor wafer or a dielectric layer overlaying the semiconducting material comprising the semiconductor wafer. The applied electrical stimulus can be a CV type electrical stimulus and the measured response can include acquiring capacitance values during application of the CV type electrical stimulus.
The semiconducting material comprising the semiconductor wafer can include an ion implanted dopant received in a test volume underlying the contact between the probe tip and the semiconductor wafer. When the probe tip contacts the dielectric layer overlaying the semiconductor material comprising the semiconductor wafer, the determining step includes the step of determining a dopant concentration in at least one layer of the test volume as a function of the acquired capacitance values.
REFERENCES:
patent: 5023561 (1991-06-01), Hillard
patent: 5767691 (1998-06-01), Verkuil
“MOS (Metal Oxide Semiconductor) Physics and Technology” by E.H. Nicollian and J.R. Brews—pp. 61-63; Copyright 1982 by Bell Telephone Laboratories, Incorporated, (month unavailable).
Hillard Robert J.
Howland William H.
Nguyen Vinh P.
Solid State Measurements, Inc.
Webb Ziesenheim & Logsdon Orkin & Hanson, P.C.
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