Method of determining dielectric time-to-breakdown

Details Method of determining dielectric time-to-breakdown Method of determining dielectric time-to-breakdown

1999-01-07

2001-02-13

Metjahic, Safet (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S762010, C257S048000

Reexamination Certificate

active

06188234

ABSTRACT:

TECHNICAL FIELD
The present invention relates, in general, to a method of stress testing a semiconductor device and, more specifically, to a method of determining dielectric reliability of a semiconductor device by measuring its dielectric time-to-breakdown.
BACKGROUND OF THE INVENTION
Ultra-thin gate dielectric breakdown is one of the main reliability concerns in Ultra Large Scale Integration (ULSI) semiconductor products. The step of determining dielectric breakdown requires a method of using accelerated life-time stress conditions. The time required to induce the breakdown is an important factor in the overall efficiency of the method. The method of stressing a gate dielectric and determining the time-to-breakdown is a cost- and time-intensive process. It is important to find methods to reduce the stress time required in determining dielectric life-time during the development phase of the semiconductor device.
The present state-of-the-art for determining dielectric reliability is based on using high temperature and high gate voltage to accelerate the mechanism of breakdown from many years, under normal operating conditions, to hours. The gate voltage has the strongest effect in accelerating the breakdown mechanism. The higher the gate voltage, the lower is time-to-breakdown. For ultra-thin gate dielectrics, below about 5 nm, the relationship between time-to-breakdown and applied voltage is linear (on a logarithmic time, linear voltage scale) up to an upper limit of gate voltage, beyond which the relationship is non-linear.
This relationship is shown in
FIG. 1
for a 4.5 nm oxide. To make accurate projections of the time-to-breakdown it is highly desirable to keep the accelerated stress voltage in the range where the relationship between voltage and time-to-breakdown is linear on a logarithmic scale. In
FIG. 1
, the time-to-breakdown deviates from a linear relationship with the gate voltage at approximately 5.8 volts. This deviation puts an upper limit on the stress voltage and, therefore, a lower limit on the time required to reach breakdown.
The problem with this conventional procedure is that the only variable available in stressing the semiconductor device is the gate voltage. The gate voltage directly determines the magnitude of gate current and the gate current (or the injected charge) has a major effect on the process of dielectric degradation leading to breakdown. A higher gate current (or injected charge) requires a lower time-to-breakdown. The problem with this stress procedure is that the gate current is not controlled independently, but rather is dictated by the applied gate voltage. Thus, the required stress time cannot be decreased below a certain time limit without compromising the accuracy of the reliability projections.
An example of a conventional gate dielectric stress system having a voltage applied to its gate dielectric is shown in FIG.
2
. As shown, an n-type field effect transistor or NFET
10
comprises a substrate
14
having a diffused source region
16
, a diffused drain region
18
, and a gate oxide region or dielectric
12
. Overlying the gate oxide region is a gate electrode
20
. The gate electrode
20
is connected to a +Vg potential reference; the drain region
18
is connected to a Vd potential reference; the source region
16
is connected to a Vs potential reference; and the substrate
14
is connected to a Vsub potential reference. V
S
, V
D
and V
SUB
are at ground potential. In this conventional system, only Vg controls the gate dielectric voltage and the amount of current injected into the gate (with the channel inverted and source and drain grounded). Because only Vg controls the gate electric field and the gate current, high values of Vg are required to reach dielectric breakdown in a reasonable time.
In a method disclosed in U.S. Pat. No. 4,382,229, issued May 3, 1983, Cottrell et al. teach that, when gate electrode
20
is biased above the threshold voltage of the NEET
10
and Vd is biased above the source voltage Vs, a channel is created between the source
16
and drain
18
and electrons flow through the channel from the source
16
to the drain
18
. Electrons flowing from the source
16
to the drain
18
are “heated” by the high electric field near the drain
18
, and a small fraction attain enough energy to surmount the energy barrier at the oxide-silicon interface and pass into the silicon oxide layer. The fraction of electrons which is emitted depends strongly on the electric field near the drain
18
and thus on the bias conditions and the device structure.
Cottrell et al. further teach that, by measuring the rate of change in gate current, the time required to achieve a predetermined change in source-to-drain current may be found. The problem with the Cottrell et al. method is that the emission current into the gate is small and applying the method to determine the time-to-breakdown of the dielectric is quite limited. Cottrell et al. teach a method for evaluating channel hot carriers in an FET, and do not address evaluation of dielectric breakdown in an FET.
In another disclosure, U.S. Pat. No. 5,615,377 issued Mar. 25, 1997 to Shimizu et al., a method of simulating hot carrier deterioration of a p-type metal-oxide semiconductor (PMOS) FET is taught. Shimitzu et al. provide a method by which a PMOS FET is forward and reverse biased. By measuring the characteristics of the PMOS FET and applying them in a simulation, Shimizu et al. estimate the deterioration of the transistor. Their teachings are limited: the method applies only to a PMOS FET and does not teach how to measure the time-to-breakdown of a PMOS FET or an NMOS FET.
In yet another disclosure, U.K. Patent Application No. 2,296,778 A, published on Oct. 7, 1996, there is disclosed a method for testing the reliability of a dielectric film on a semiconductor substrate. The method applies a gate current which is increased in successive steps until the dielectric film breaks down. A disadvantage of this method is that, in order to increase the gate current, the gate voltage must also be increased. Gate current cannot be independently controlled from gate voltage.
The method also does not work in ultra-thin dielectrics, because a very high stress field must be applied until breakdown occurs. Applying a high electric field to the gate results in inaccuracies in determining the dielectric reliability. At high electric fields the relationship between applied gate voltage and the time-to-breakdown is non-linear on a logarithmic scale, thereby causing errors in extrapolating the results to determine the time- to-breakdown.
Another method is taught by H. Ning et al. in Journal of Applied Physics, Volume 48, page 286 (1977). A negative, or reverse bias is applied to Vsub and a positive, or forward bias, is applied to Vg with Vs and Vd both at a ground potential (refer to FIG.
2
). A tungsten light bulb (not shown) supplies photons into the gate lectrode
20
and gate dielectric
12
, which in turn generates electron-hole pairs in substrate
14
. The electrons gain energy from the electric field, as they drift toward the interface between the substrate
14
(silicon) and the gate dieletric
12
(silicon dioxide) . The electrons arriving at the interface with sufficient energy are emitted into the gate dielectric
12
. These emitted electrons are collected as the gate current. The method taught by H. Ning et al. requires two reference voltages, Vg and Vsub, as well as a light energy source. Vg and Vsub cannot supply enough electrons into the gate, however, because Vg and Vsub are kept at low reference potentials. Furthermore, this method is not feasible for integrated processing applications where the semiconductor is covered by back-end-of-line (BEOL) dielectrics and metals.
The deficiencies of the conventional methods show that a need still exists for a method to measure the dielectric time-to-breakdown of an FET transistor that does not require a high gate voltage. To overcome the shortcomings of the conventional methods, a new method is provided of determining d

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