Static information storage and retrieval – Floating gate
Reexamination Certificate
1999-12-09
2001-04-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
C365S185100
Reexamination Certificate
active
06222759
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to modeling the characteristics of a semiconductor device. More particularly, the invention relates to modeling characteristics of an electrically-erasable programmable read-only memory (EEPROM).
2. Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM) is an electronic memory device that stores information in the form of the presence or absence of electronic charge on a floating gate.
The gate is “floating” because it is surrounded by an insulating material, and no electrical contact is made to it. Thus, charge placed on the floating gate will remain and will not leak off the gate over time, even when power to the device is removed. Accordingly, this type of memory is nonvolatile. To place charge on the floating gate, the device must perform a programming sequence that forces charge across the insulating material.
EEPROM cells can take various forms. One such form is a “split gate” cell that is characterized by an overlapping arrangement of a control gate and the floating gate. With this arrangement, both the control gate and the floating gate have a strong influence on electron flow from the device's source to its drain. Another form is a double-poly single-transistor erasable tunnel oxide (ETOX) cell, which uses two gates aligned vertically, so that the control gate is spaced far apart from the device body.
Routines to program, erase, and read an EEPROM are well-known. For example, one such routine programs the cell (or performs a write operation) by placing a negative charge on the floating gate by hot electron injection. Hot electron injection involves raising a drain (D) voltage relative to a source (S) voltage to a sufficiently positive value. Then, the control gate (CG) voltage is raised relative to the source voltage to a sufficiently positive value. This causes electrons to flow in the channel under the control gate and the floating gate, from source to drain. The electric field set up by the control gate attracts these elections. Because of the high drain voltage, the electrons are very energetic, i.e., “hot.” Some of the hot electrons are energetic enough to cross the thin insulating oxide under the floating gate. As a result, electrons are injected onto the floating gate.
Erasing, or removing, charge from the floating gate involves the steps of raising the substrate “body” (B) voltage to a sufficiently positive value and grounding the source, control gate, and drain. The electric field set up by the body voltage causes electron flow from the floating gate to the substrate.
After charge is placed on or removed from the cell, the cell is read to determine its state. When reading the cell, voltages are applied to the cell in the manner of an ordinary MOSFET. Accordingly, positive voltages, which are smaller in magnitude than the programming/writing or erasing voltages, are put on the drain and control gate and the amount of current that flows from source to drain is measured.
The absence of charge on the floating gate is typically assigned to be a high logic state, e.g., a “1”. In this state, the cell is fully conductive. On the other hand, when charge is present on the floating gate, the cell will be less conductive during a read operation. The presence of charge on the floating gate is typically assigned to be a low logic state, e.g., a “0”. In this state, the cell is partially, or completely, non-conductive.
The cell could also be programmed in a multi-bit manner. In such a multi-bit programming scheme, the amount of charge on the floating gate will set the cell in one of more than 2 states.
The operational characteristics of an EEPROM cell depend primarily on geometrical factors, for example, the distances between the electrodes. After a device is constructed, the geometry of the device is difficult to measure.
When designing a conventional EEPROM, measurements of capacitance have been used as a proxy for direct physical measurements. Capacitance measurements can be interpreted to provide an indication of the physical dimensions of the device and, thus, the actual electronic performance of the device. Typically, the measurements are used to determine “coupling capacitances,” which describe the influence of an electrode on another electrode. Ratios of these capacitances, known as coupling ratios, may also be used to describe an EEPROM cell. These coupling ratios not only help to monitor the floating gate but also provide an indication of the voltage drop between a gap region, which is a weak control region between control gate and floating gate, and the floating gate. Once the electronic performance of the device is modeled, the model can be used to determine the voltage of the floating gate, something that cannot be done with a direct measurement.
Conventional design programs, such as HSPICE, used in conjunction with determined coupling ratios are used to model a device. With an accurate model, cell design can be enhanced, thereby preventing malfunction. Accordingly, a device could then be designed with a small safety tolerance.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a model for the characteristics of a semiconductor device, a cell designed using such a model, and a method for modeling such characteristics that substantially obviate one or more of the problems due to limitations and disadvantages of the prior art. To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention comprises a method of determining characteristics of a split-gate memory cell, including substantially fully charging a floating gate, measuring a parameter of the memory cell while the floating gate is substantially fully charged, and determining a characteristic of the memory cell based on the measurement.
In another aspect, the present invention provides a method of determining a characteristic of a split-gate memory cell, including initializing the memory cell, placing the memory cell in a reverse operation mode, sweeping a control gate voltage of the cell, measuring a source voltage of the cell, and determining the characteristic of the memory cell.
Also, the present invention provides a method of determining two characteristics of a split-gate memory cell, including defining a first function having three unknown variables, the two characteristics being two of the unknown variables, defining a second function where only the two characteristics are unknown variables, measuring a first device parameter relative to a second device parameter to determine the remaining unknown variable of the first function, and solving for the first function and second function using the measurement to determine the two characteristics.
Additional advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the embodiments of the invention and together with the description, serve to explain the principles of the invention.
REFERENCES:
patent: 5268318 (1993-12-01), Harari
patent: 5835409 (1998-11-01), Lambertson
patent: 6005809 (1999-12-01), Sung et al.
patent: 6058043 (2000-05-01), Houdt et al.
Noren et al., “Macromodel Development for a FLOTOX EEPROM,” IEEE Transactions on Electron Devices (Jan. 1998), 45:224-229.
Brown et al., “Nonvolatile Semiconductor Memory Technology,” Institute of Electrical and Electronics Engineers, Inc. (1998), pp. 54-60.
Wong et al., “Analysis of the Subthreshol
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Le Thong
Nelms David
Winbond Electronics Corporation
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