Method of detecting the width of lightly doped drain regions

Details Method of detecting the width of lightly doped drain regions Method of detecting the width of lightly doped drain regions

1989-11-30

1990-12-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 8, 437 41, H01L 2166, H01L 21265

Patent

active

049786270

ABSTRACT:
A process for fabricating field effect transistors with lightly doped drain (LDD) regions having a selected width includes a method of optically detecting the width of spacers used to mask the LDD regions during the source and drain implant and a method of electrically determining (confirming) the width of the LDD regions. In the optical method, reference structures are formed concurrently with the fabrication of the gates for FETs, a spacer material is formed on the substrate, the gates and the reference structures, the spacer material is etched away and the width of the spacers is optically detected by aligning the edges of spacers extending from two reference structures separated by a known distance. In the electrical method, the width is determined by defining a test area with known dimension, forming both N.sup.+ and N.sup.- regions in the test area, measuring the resistance across the test area, calculating the resistance of the N.sup.+ and N.sup.- regions, and calculating the width of the N.sup.- region from the resistance of the N.sup.- region. The electrically determined width is compared with the desired LDD region width, and the difference between the electrically determined width and the desired width is used to adjust the distance between the reference structures for a subsequent processing run.

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