Pulse or digital communications – Testing
Reexamination Certificate
1998-02-11
2001-10-30
Chin, Stephen (Department: 2634)
Pulse or digital communications
Testing
C375S227000, C375S228000, C714S048000, C714S704000, C370S241000, C370S242000
Reexamination Certificate
active
06310911
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method of detecting signal degradation fault conditions in synchronous digital signals, for example within SONET and SDH signals.
BACKGROUND OF THE INVENTION
SONET (Synchronous Optical Network) is a physical layer standard for fiber optic transmissions. SDH (Synchronous Digital Hierarchy—is an international standard of optical signals, payload formatting, and operations. Within the overheads of the various signal types that are defined within the SONET and SDH standards, there are bytes that are dedicated for use as bit interleaved parity checks (BIPs). By counting the number of BIP errors that are detected when such a signal is received, an estimate for the actual line error ratio can be obtained. While the correspondence between the number of BIP errors detected and the actual line bit error ratio has been documented, little (if any) guidance is presented as to how these relationships can actually be incorporated into an algorithm that facilitates the implementation of such a system.
The manner in which the signal degrade fault condition is monitored involves the integration of the number of BIP errors detected over time and comparing the result to a pre-determined threshold value. Should this number of errors exceed the threshold for the signal degrade fault condition, then it can be stated that the condition exists. A complication introduced by the SONET/SDH requirements is that they dictate the detection time for any line bit error ratio must be a factor of the actual bit error ratio, and not a factor of the signal degrade threshold that is being used. As such, it is necessary to monitor for multiple bit error ratios concurrently and make decisions concerning the presence (or absence) of signal degrade based on these results. This is typically accomplished by polling the received BIP error counts at a rate which is at least half of the required detection time for the highest bit error ratio to be monitored, and to maintain a history of these samples for a duration of time that is equal to the required detection time of the lowest bit error ratio.
The aforementioned technique is simple and effective but given the wide range of bit error ratios that must be monitored (1E-5 to 1E-10) and their associated detection times, the amount of memory needed to maintain a sample history of the appropriate length can get quite large. While this may not prove to be an issue for applications that have large memory resources, it can be paramount to those applications with smaller, fixed memory resources.
An object of the present invention is to address the issue of excessive memory usage that a typical application would require.
SUMMARY OF THE INVENTION
According to the present invention there is provided a method of detecting signal degradation conditions in synchronous digital signals, comprising the steps of detecting the presence and/or absence of particular bit error ratios by integrating received parity errors over time in a plurality of bit error monitors, and reacting to notifications from bit error rate monitors that the state of the presence/absence of specific bit error ratios has changed to take a predetermined action depending on the state of the monitors.
In the invention, the functionality required to detect signal degradation is broken down into two distinct entities. The first, referred to as the bit error rate monitor, is solely responsible for detecting the presence and/or absence of a particular bit error ratio from integrating received parity errors over time (note that multiple instances of this monitor can be used to detect different error rates simultaneously). The second entity, referred to as the bit error rate monitor client, is responsible for reacting to notifications from bit error rate monitors that the state of the presence/absence of specific bit error ratios has changed.
In addition, the polling of receive error counts needs only be done at a single interval by a single polling application.
Any bit error rate monitor can be used to watch for a specific bit error ratio in a received signal. In order to accomplish this, it needs to be configured properly and supplied with samples of error counts at regular intervals (i.e. via polling). Within the bit error rate monitor there is a state machine whose intent is to keep track of whether the monitor is currently detecting a bit error ratio that is either equal to or greater than its currently programmed monitored bit error ratio (the “equal to or exceeded” state), or is less than this ratio (the “less than” state). Also within the object is a queue of parity error count samples that is used to integrate the number of errors that have occurred over a fixed length of time (expressed as an integer number of samples). This integration is accomplished using a sliding window technique.
Every time a new error count sample is received, the value at the head of the sample queue is removed and subtracted from the total number of errors that have been accumulated over the width of the integration window. The new sample is then inserted at the tail of the queue and added to this accumulated total. This new total is then compared to the parity error count threshold value and if it is less than the threshold, the bit error rate monitor is deemed to be in the “less than” state. If it is equal to or greater than this threshold, then it is in the “equal to or exceeded” state.
A unique side effect of the fact that the bit error rate monitors are provided with parity error count samples (rather than being responsible for obtaining their own) is that it is not necessary that this sample be provided from a hardware register of a parity checking device. In fact, it is possible that this parity error count sample can be provided by another instance of a bit error rate monitor. As a result, the concept of an “upper monitor” can be introduced whereby a bit error rate monitor can be configured to supply its “upper monitor” (another instance of a bit error rate monitor) with parity error count samples determined from the error count samples that it is supplied with. By supplying the “upper monitor” with the sum of every n error count samples, the “upper monitor” is effectively being supplied with the same parity error counts as the bit error rate monitor, except at n times the sampling rate. This allows multiple bit error monitors to be linked together in order to detect the presence of several different bit error rates simultaneously.
The invention also provides an apparatus for detecting signal degradation conditions in synchronous digital signals, comprising a plurality of monitors for detecting the presence and/or absence of particular bit error ratios by integrating received parity errors over time; and a bit error rate monitor client responsive to outputs from said plurality of monitors to take a predetermined actions depending on the state of said plurality of bit error monitors.
REFERENCES:
patent: 4375102 (1983-02-01), Van Daal
patent: 5138616 (1992-08-01), Wagner, Jr. et al.
patent: 5271011 (1993-12-01), McMullan, Jr. et al.
patent: 5418789 (1995-05-01), Gersbach et al.
patent: 5467341 (1995-11-01), Matsukane et al.
patent: 5606563 (1997-02-01), Lee
patent: 5621737 (1997-04-01), Bucher
patent: 5627837 (1997-05-01), Gillett
patent: 5724362 (1998-03-01), Lau
patent: 5764651 (1998-06-01), Bullock et al.
patent: 5886842 (1999-03-01), Ziperovich
patent: 6073257 (2000-04-01), Labonte et al.
Zhand Xiaoru; Zneg Lieguang: “Performance analysis of BIP codes in SDH on Poisson distribution of errors.” Communication Technology Proceedings, ICCT '96, 1996 May 5-7, 1996, pp. 829-832, XP002146479 the whole document.
Burke Dan
Jennings Alan
(Marks & Clerk)
Alcatel Canada Inc.
Chin Stephen
Ha Dac V.
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