Method of detecting and indicating errors in a memory device

Details Method of detecting and indicating errors in a memory device Method of detecting and indicating errors in a memory device

1990-08-20

1991-09-24

Atkinson, Charles E.

Excavating

371 6, 371 214, G06F 1110

Patent

active

050520024

ABSTRACT:
An EEPROM system with an error detecting function includes: a memory cell matrix composed of a plurality of MOS memory cells and a plurality of bit lines connected separately to the plurality of MOS memory cells; and a plurality of intermediate state detecting circuits connected separately to the plurality of bit lines for detecting an intermediate state other than writing and erasing states of the MOS memory cells, and for outputting an error bit indicating signal, the intermediate state being a threshold voltage between a threshold voltage of a storage MOS memory cell in a writing state included in each of the MOS memory cells and a threshold voltage of the storage MOS memory cell in an erasing state.

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IEEE Transactions on Reliablity, vol. R36, No. 2, Jun. 1987, pp. 222-223, T. Haifley, "Endurance of EEPROMs with On-Chip Error Correction".

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