Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
1998-08-07
2002-01-22
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S338000, C257S369000
Reexamination Certificate
active
06340825
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of designing a semiconductor integrated circuit device, and a technique effective in a case in which a plurality of circuits different in characteristic from each other are prepared as a cell library and a user selects a desired circuit from the cell library in the course of design of a semiconductor integrated circuit device. This invention also relates to a technique which is effective for use in the design of an ASIC (Application Specific Integrated Circuit), for example.
It has been known that a semiconductor logic integrated circuit device principally using field effect transistors like MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) is capable of operating at high speed as the threshold voltage of each MOSFET decreases; whereas, since a substantial leakage current is produced during its off state when the threshold voltage thereof is low, the use of a semiconductor logic integrated circuit device will lead to an increase in power consumption. As a characteristic of each MOSFET, a so-called substrate bias effect is known, wherein the threshold voltage thereof will go high as a reverse bias voltage between the source thereof and a base (substrate or well region) increases. Further, a technique for controlling a standby current has been described in Japanese Published Unexamined Patent Application No. Hei 7-235608, for example.
SUMMARY OF THE INVENTION
A technique, wherein an inverter circuit or an inverter INV, capable of switching the potentials of bases (n well and p well) to a source voltage Vcc and a reference voltage Vss, and base or substrate bias voltages Vbp (Vbp>Vcc) and Vbn (Vbn>Vcc), as shown in FIGS.
21
(A) and
21
(B), is used in place of an inverter INV wherein the potentials of bases (n well and p well) shown in FIGS.
20
(A) and
20
(B) are fixed to a source voltage Vcc and a reference voltage Vss (Vcc>Vss), respectively, has been described in, for example, “ISSCC Dig. of Tech. Papers”, pp. 166-167, 437, February 1996, or IEEE CICC, pp. 53-56, May 1996.
According to this technique, the source voltages Vcc and Vss are applied to the bases (n well and p well) when the circuit is in operation (active), to thereby supply a low reverse bias voltage between the source and substrate or base, whereby each MOSFET is set to a low threshold so as to operate the circuit device at high speed. On the other hand, when the circuit is deactivated (at standby), the substrate bias voltages Vbp and Vbn are applied to the bases (n well and p well) to supply a high reverse bias voltage between the source and the base (well), thereby increasing the threshold of each MOSFET to reduce the leakage current, whereby low power consumption is provided. The present inventors have discussed the semiconductor integrated circuit device using MOSFETs capable of performing switching to the subtrate bias voltages. As a result, it became evident that the following problems were inherent in such a device.
When the threshold of each MOSFET is controlled using the above described substrate bias effect in an attempt to realize an IC having desired characteristics, an inconvenience occurs in that wiring or wires for supplying the bias voltages to the well regions used as the bases of the respective MOSFETs are required in large numbers (Vcc line, Vbh/Vcc line, Vss line and Vbn/Vss line) and the area occupied by the circuit, and, in turn, the chip size of the IC, increases.
The development of an ASIC or the like will call for consideration of two cases: a first case where a user desires an IC having low power consumption or reduced chip size even if its operating speed is slow; and a second case where the user desires an IC capable of operating at high speed even if the power consumption increases more or less. When the reverse bias voltage between the source and base (well) is increased or decreased in an attempt to realize the above-described ICs which are different in characteristic from each other, a maker must separately design substrate potential fixed circuit cells and substrate potential variable circuit cells suitable for the respective ICs and prepare them as separate cell libraries. Therefore, the design effort increases, and the labor, such as the extraction of characteristics including delay times or the like of the circuit cells, required when the user designs and evaluates the chip using these circuit cells, the description thereof in the specifications (data sheet or data book), etc. also increases, i.e., the burden of preparing respective specifications for corresponding cell libraries increases.
An object of the present invention is to provide a design technique capable of implementing ICs which are different in cell type from each other without having to increase the burden on the designer.
Another object of the present invention is to provide a design technique capable of easily implementing a semiconductor integrated circuit device in which its chip size, power consumption and operating speed are optimized.
The above, other objects and novel features of this invention will become apparent from the description provided by the present specification and the accompanying drawings.
A summary of a typical one of the features disclosed in the present application will be described as follows:
Design information about circuit cells each having a desired function are described as objects according to desired purposes and are registered in a cell library registered with a plurality of circuit cells for forming ASIC or the like as design resources in the form of cell information capable of forming any of substrate potential fixed and variable cells by only the deletion or addition of information about predetermined objects. Incidentally, the present cell library is stored in a storage medium such as a magnetic disc, an optical disk, a printed material or the like.
As a typical one of the above-described circuit cells, a cell is known which comprises a pair consisting of a p channel MOSFET and an n channel MOSFET constituting a CMOS inverter which falls under the designation of a minimum unit in a circuit, for example. Others used as the circuit cells registered in the cell library may include a basic circuit cell, such as a flip-flop, a NOR gate, a NAND gate or the like, as frequently used in a logic LSI, a CPU peripheral circuit module, such as a CPU core used as a control circuit, a random access memory used as a memory circuit, a timer, a serial communication interface circuit or the like, and a macrocell like an A/D converter, a D/A converter or the like used as a signal processing circuit.
According to the above feature, since only one kind of cell may be designed for circuits having the same function, a maker can reduce the burden on the design and labor, such as the extraction of characteristics such as voltage dependency, temperature dependency, delay times or the like of each designed cell, the description thereof in the specifications, etc., and, in its turn, achieve a reduction in cost as well.
Further, a semiconductor integrated circuit device wherein the chip size, power consumption and operating speed are optimized, can easily be implemented by properly using substrate potential fixed and variable cells according to the functions or the like of circuit portions used with cells on one semiconductor chip and mixing them together in this condition.
Typical ones of various features of the present invention have been described in brief. However, the various embodiments of the present invention and specific configurations of these embodiments will be more fully set forth in the following description.
REFERENCES:
patent: 5105252 (1992-04-01), Kim
patent: 5311048 (1994-05-01), Takahashi
patent: 5376839 (1994-12-01), Horiguchi
patent: 5434436 (1995-07-01), Taniguchi
patent: 5801407 (1998-09-01), Yamada
patent: 2269049 (1994-01-01), None
patent: 63-090847 (1988-04-01), None
patent: 6-085200 (1994-03-01), None
patent: 6-120439 (1994-04-01), None
patent: 6-334010 (1994-12-01), None
patent: 7-235608 (19
Shibata Ryuji
Shimada Shigeru
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Jackson, Jr. Jerome
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