Method of designing semiconductor integrated circuit apparatus h

Details Method of designing semiconductor integrated circuit apparatus h Method of designing semiconductor integrated circuit apparatus h

1995-03-15

1997-10-07

Teska, Kevin J.

Boots, shoes, and leggings

364491, H01L 2350

Patent

active

056755015

ABSTRACT:
A method of designing a semiconductor integrated circuit apparatus vice comprises: a placement step of generating row information indicating a transistor row in which transistors required for the configuration of a transistor row to be designed are placed so that wiring length is as short as possible on the basis of net connection information of transistors, size information of various transistors constituting the net, and ideal module size information which provides constraint relating to sizes in X-direction and sizes in Y-direction perpendicular to the X-direction of the transistor row in which the various transistors are arranged in the X-direction; a row size determination step of generating, on the basis of the row information, row size information indicating sizes in the X-direction and the Y-direction of the transistor row that the row information indicates; and a parallel arrangement step of carrying out parallel arrangement of transistors constituting the transistor row so that the transistor row that the row information indicates falls within sizes in X-direction and Y-direction that the row size information indicates.

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IEEE 1992 Custom Integrated Circuits Conference, pp. 11.1.1-11.1.4, 1992, Stan Chow, et al., "The Layout Synthesizer: An Automatic Block Generation System".
ICCAD, pp. 340-343, 1989, Antun Domic, et al., "CLEO: a CMOS Layout Generator".

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