Boots – shoes – and leggings
Patent
1994-11-10
1996-11-26
Teska, Kevin J.
Boots, shoes, and leggings
364490, G06F 1710
Patent
active
055792375
ABSTRACT:
An integrated circuit placement method is executed according to a mini-cut method to design the cell placement of an integrated circuit by setting a cut line which divides the integrated circuit into a plurality of blocks and moving the cells such that the cut size, that is, the number of nets, connecting the cells and traversing the cut line can be minimum. It aims to determine the optimum placement by preventing cut size from keeping a local minimum state. A first process P1 detects stable nets which have caused a local minimum state if the cut size in a net has reached the local minimum state after executing the mini-cut method. A second process P2 selects all or a part of the detected stable nets and moves the cells connected to the selected stable nets and placed in different blocks to either of the blocks. A third process P3 detects stable nets if it is determined that the cut size of the net cannot satisfy a terminate condition after executing the mini-cut method immediately following the second process P2, and reactivates the second process P2.
REFERENCES:
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4593363 (1986-06-01), Burstein et al.
patent: 5113352 (1992-05-01), Finnerty
patent: 5144563 (1992-09-01), Date et al.
patent: 5159682 (1992-10-01), Toyonaga et al.
patent: 5189784 (1993-02-01), Rowson
patent: 5224056 (1993-06-01), Chene et al.
patent: 5224057 (1993-06-01), Igarashi et al.
patent: 5257201 (1993-10-01), Berman et al.
patent: 5267176 (1993-11-01), Antreich et al.
patent: 5308798 (1994-05-01), Brasen
patent: 5349536 (1994-10-01), Ashtaputre et al.
patent: 5359538 (1994-10-01), Hui et al.
Yang et al., "Two-level partioning algorithm with stable performance", IEEE Proc. Circuit Dev. Sys., vol. 14, No. 3, Jun. 1994, p. 197-202.
Tragoudas, "An Improved Algorithm for the Generalized Min-Cut partitioning Problem", IEEE 1994, p. 242-247.
Shin et al., "A Simple Yet Effective Technique for Partitioning", IEEE Trans on VLSI Sys, vol. 1, No. 3, Sep. 1993, pp. 380-386.
Cheng et al., "An Improved Two-Way Partitioning Algorothm with Stable Performance", IEEE Trans on CAD, vol. 10, No. 12, Dec. 1991, p. 1502-1511.
Tragoudas, "Min Max-Cut Graph Partitioning problems" IEEE 1993, pp. 100-104.
Zhou et al., "An Asymptotically optional Algorithm for Gate Array Placement", IEEE 1993, pp. 95-98.
Sriram et al., "A Parallel Min-Cut Technique for Standard Cell Placement Using Modified Hopfield Neural Network", China 1991 Int'l Conf on Circ. & Sys, Jun. 1991, 894-897.
Ball et al., "Fuzzy Partioning applied to VLSI-Floorplanning & Placement", pp. 177-180.
Terai, "A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint", IEEE 1990 27th ACM/IEEE DAC, pp. 96-102.
Hill, "Alternative Strategies for Applying Min-Cut to VLSI Placement", IEEE 1988, pp. 440-444.
Leighton et al., "An Approximate Max-Flow Min-Cut Theorem for Uniform Multicommodity Flow Problems with Applications to Approximation Algorithms", IEEE 1988, pp. 422-431.
Krishnamurthy, "An Improved Min-Cut Algorithm For Partitioning VLSI Networks", IEEE Trans on Computers, vol. 33, No. 5, May 1984, 438-446.
Vijayan, G, "Generalization of Min-Cut Partitioning to Tree Structures and Its Applications", IEEE Trans on Computers, vol. 40, No. 3, Mar. 1991, 307-314.
Fujitsu Limited
Teska Kevin J.
Walker Tyrone V.
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