Method of design and fabrication of integrated circuits...

Details Method of design and fabrication of integrated circuits... Method of design and fabrication of integrated circuits...

2001-09-13

2004-11-16

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Plural exposure steps

C430S312000, C430S396000

Reexamination Certificate

active

06818389

ABSTRACT:

FIELD OF THE PRESENT INVENTION
The present invention is directed to the fabrication of integrated circuits using arrays, gratings, and/or laser interferometry. More particularly, the present invention is directed to a process and methodology of fabricating integrated circuits that accounts for both optical proximity and spatial frequency effects while maintaining the resolution-enhancement characteristics required by sub-wavelength lithography.
BACKGROUND OF THE PRESENT INVENTION
Conventional optical projection lithography has been the standard silicon patterning technology for the past 20 years. It is an economical process due to its inherently high throughput thereby providing a desirable low cost per part or die produced. A considerable infrastructure (including steppers, photomasks, resists, metrology, etc) has been built up around this technology.
In this process, a mask, or “reticle”, includes a semiconductor circuit layout pattern typically formed of opaque chrome, on a transparent glass (typically SiO
2
) substrate. A stepper includes a light source and optics/lenses that project light coming through the reticle and image the circuit pattern, typically with a 4× to 5× reduction factor, on a photo-resist film formed on a silicon wafer. The term chrome refers to an opaque masking material that is typically but not always comprised of chrome. The transmission of the opaque material may also vary such as in the case of an attenuating phase shift mask.
FIG. 1
is an example of a conventional optical projection lithography apparatus. As illustrated in
FIG. 1
, the optical projection lithography apparatus includes a light source
20
, a photomask
22
, and reduction optics
24
. A wafer
26
, having a layer of photo-resist
28
thereon, is placed within the optical projection lithography apparatus, and the light-source
20
generates a beam of light
21
that is incident upon the photomask
22
. The reduction optics
24
reduces the light beam to cause a pattern
30
that exposes the photo-resist layer
28
, creating the pattern
30
of reacted material in the resist layer
28
. In this manner, a pattern
32
, provided on the mask
22
, is transferred to the photo-resist layer
28
on the wafer
26
.
The photo-resist pattern
30
is then transferred to the underlying wafer
26
through standard etching processes using standard semiconductor fabrication techniques. Both positive and negative tone resists can be used to produce either positive or negative images of the mask pattern on the wafer.
As the semiconductor industry continues to evolve and grow, feature sizes of the pattern are driven to an ever-smaller resolution. The driving force is the desire of these industries to remain on the “Moore's Law” growth curve. The “Moore's Law” growth curve calls for an exponential increase of circuit density versus production year that is typically accomplished by decreasing feature sizes. However, the resolution of an optical stepper is limited by the wavelength of the light source, and is further limited by the numerical aperture (“NA”) of the lens.
The basic lithographic imaging relationships are:
1) Resolution=k
1
/NA; and
2) Depth of Focus=k
2
/(NA)
2
;
where is the illumination wavelength, NA is the lens numerical aperture, and k
1
and k
2
are process constants.
In general, a shorter wavelength light source and/or a higher numerical aperture lens affords a higher-resolution system. State-of-the-art light sources provide a beam having a wavelength of approximately 193 nanometers. As stated above, the semiconductor industry has been driving the need for critical feature sizes to decrease exponentially over time while exposure light sources have only been decreasing linearly with time.
Carrying this scenario forward, current and future optical lithography will be required to image feature sizes of sub-wavelength dimensions. Sub-wavelength optical lithography has been realized with the 180-nm device generation fabricated using 248-nm optical lithography.
As noted above, the numerical aperture of the lens also drives resolution. In this field, the cost of lenses having very high numerical apertures (“NA”) approaching 0.8 is very high. Moreover, linear NA increases are not sufficient to maintain pace with the need for exponentially decreasing feature sizes.
To meet this demand, Resolution-Enhanced optical lithography Technologies (“RET”) have become popular as techniques for providing patterns with sub-wavelength resolution. These methods include off-axis illumination (“OAI”), optical proximity correction (“OPC”), and phase-shift masks (“PSMs”). Such resolution-enhanced optical lithography methods are especially useful for generating physical devices on a wafer that require small size and tight design tolerance. Examples of such physical devices are the gate length of a transistor or the dimensions of contact cuts formed in inter-layer dielectrics. However, the conventional RET methods face problems with layout complexity and data size, mask fabrication complexity and resulting cost, and optical proximity effects (CUT effects) and spatial frequency effects which are discussed below.
In many circuit applications, it is an important design constraint that the respective sizes of the narrow lines are consistent throughout the circuit. For example, in a semiconductor device, the narrow lines may form transistor gates, and it is important that the transistor gates are similar in size so that the circuit has consistent and predictable gate delay values.
In general, in any optical lithography technique, the resulting optical image intensity is a function of the proximity of features. Contrast is lost as feature pitch values decrease. As a result, the resulting size of features located in densely populated regions can be different than the size for those features that are isolated from the densely populated features. This is known as the “optical proximity” effect.
With respect to optical proximity effect, the critical dimension of features depends on feature density. Moreover, optical proximity effects can become more severe in sub-wavelength lithography. The optical proximity effects can result in dense lines
261
and isolated line
262
on wafer
26
being printed with different sizes, even if the same size on the mask, as illustrated in
FIG. 2
, or dense contacts
263
and isolated contact
264
on wafer
26
being printed with different sizes, even if the same size on the mask, as illustrated in FIG.
3
. Since the performance of the circuit depends on the size and size tolerance of the gates, this is an undesirable result.
Spatial frequency effects are caused by the “low-pass filter” behavior of a projection lithography lens wherein high spatial frequencies do not pass through the lens. This results in corner rounding and line end shortening. An example of this effect is illustrated in FIG.
4
. As illustrated in
FIG. 4
, a desired image is represented by mask
220
, but the actual image pattern
265
on the wafer is shortened and rounded.
To compensate for optical proximity and spatial frequency effects, additional features have been conventionally introduced on the mask that can involve both printable as well as sub-resolution elements. In these methods, extra features such as serifs, mousebites, hammerheads, and scattering bars are added to the mask features in order to correct for optical proximity effects and other spatial frequency effects. These conventional methods involve sophisticated algorithms with very large data size, as different corrections are required for each separation distance between the features. For this reason, conventional feature size correction (“OPC” or optical proximity correction) is a costly and time-consuming process.
Conventional OPC generally involves the processing of an enormous data volume. The hierarchical data processing algorithms used for conventional circuit design are of limited utility because optical proximity effects are based on the nature of geometries surrounding a particular circuit element. Fo

Affiliated with

Also associated with

Rating

Method of design and fabrication of integrated circuits... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of design and fabrication of integrated circuits..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of design and fabrication of integrated circuits... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3286744