Method of delaying digital signals

Details Method of delaying digital signals Method of delaying digital signals

1978-10-02

1981-04-28

Heyman, John S.

Registers

Coded record sensors

Particular sensor structure

328 37, 328 48, 235 92SH, H03K 5159, H03K 2136

Patent

active

042648653

ABSTRACT:
A method of delaying a signal N period lengths of a timing signal is disclosed using two shift registers which have capacities y and z, each less than N, but which have a total capacity greater than N. The signal to be delayed is fed to a first shift register until that shift register is full. The signal is later fed to the second shift register. When N bits of information have been recorded by the shift registers, the first shift register is again inputted causing an output which corresponds to the first data bits of the signal. Thus, there is stored in both registers y+z-N bits of common data during each cycle. This cycle is repeated for each N periods of the timing signal, thereby resulting in the storage of N data bits by a plurality of shift registers which each have a capacity less than N which have a total capacity greater than N.

REFERENCES:
patent: 3044065 (1962-07-01), Barney et al.
patent: 3096483 (1963-07-01), Ransom
patent: 3588707 (1971-06-01), Manship
patent: 3675049 (1972-07-01), Haven
patent: 3851154 (1974-11-01), Beecham
patent: 3941982 (1976-03-01), Knollenberg et al.

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