Semiconductor device manufacturing: process – Forming schottky junction
Patent
1995-11-13
1997-09-16
Powell, William
Semiconductor device manufacturing: process
Forming schottky junction
216 39, 216 41, 438572, 438582, 438585, 438590, 438692, 438699, H01L 2100, B44C 122
Patent
active
056676328
ABSTRACT:
A method of defining a line width includes forming a spacer (45) over a layer (42) and using the spacer (45) as an etch mask (57) while etching the layer (42). In this manner, a width (47) of the spacer (45) is used to define a width or line width (47) for the layer (42). Another method of using a spacer to define a line width includes forming a spacer (14) over a substrate (11), depositing a layer (15) over the substrate (11) and the spacer (14), planarizing the layer (15) to expose the spacer (14), and removing the spacer (14) to form an opening (19) over the substrate (11), wherein the opening (19) has a width or line width (17) of the spacer (14).
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Tohru Nishibe, J. Vac Sci. Technol.B 13(4), "Novel fabrication process utilizing thermal stress for uniform ultrafine SiO.sub.2 gaps with perfectly vertical sidewalls", Jul./Aug. 1995, pp. 1429-1433.
Burton Richard S.
Grivna Gordon M.
Chen George C.
Motorola Inc.
Powell William
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