Method of decoupling the high order portion of the addend from t

Details Method of decoupling the high order portion of the addend from t Method of decoupling the high order portion of the addend from t

1995-11-30

1998-05-26

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

057576866

ABSTRACT:
A method and apparatus for decoupling the high order portion of the addend from the multiply result in an FMAC (floating-point multiply accumulate unit) such that the FMAC's datapath width is bounded to "2m+1"-bits, and the maximum width of required adders, shifters and leading bit anticipators is also bounded to "2m+1"-bits. The method and apparatus 1) reduce the necessary chip area for implementing an FMAC, and 2) reduce the length of routing paths through adders and shifters.

REFERENCES:
patent: 4926369 (1990-05-01), Hokenek et al.
patent: 4969118 (1990-11-01), Montoye et al.
patent: 5375078 (1994-12-01), Hrusecky et al.
patent: 5530663 (1996-06-01), Garcia et al.
IBM Journal of Research and Development, vol. 34, No. 1, Jan. 1990 (specifically, pp. 59-77).

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