Method of debugging a 3D packaged IC

Details Method of debugging a 3D packaged IC Method of debugging a 3D packaged IC

2006-09-26

2006-09-26

Hollington, Jermele (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

07112981

ABSTRACT:
In a method of testing a 3D packaged IC, the dies are tested under power by mounting on a specifically designed printed circuit board with a window in it for testing the die sequentially from below using a laser beam tester. The die found not to be defective is partially removed in sequential manner to allow the next higher die to be tested. The partial removal of dies is achieved by grinding a window in them using “ChipUnzip” techniques.

REFERENCES:
patent: 6137295 (2000-10-01), Yoshida
patent: 6753524 (2004-06-01), Matsui et al.

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