Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2002-10-03
2004-05-11
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S599000
Reexamination Certificate
active
06734046
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
Embodiments of the present invention generally relate to generating chip layout designs. More particularly, embodiments of the present invention relate to generating the padring layout design.
2. Related Art
Typically, the integrated circuit (or chip) design process begins with a specification which describes the functionality of the chip and may include a variety of constraints. Then, during a logic design phase, the logical implementation of the integrated circuit is determined. Several operations are performed to obtain a logical representation of the integrated circuit. Generally, EDA software tools use register transfer logic (RTL) to represent the integrated circuit. However, additional EDA software tools may be used.
After completing the logic design phase, the chip undergoes a physical layout design phase. Typically, the output of the logic design phase is a netlist, which is then used in the physical layout design phase. Here, EDA software tools layout the integrated circuit to obtain a layout representation of the physical components in the integrated circuit, whereas the layout representation indicates the manner in which the integrated circuit will be fabricated on a semiconductor wafer. A variety of operations are performed on the layout of the integrated circuit.
At the end of the physical layout design phase, the final layout representation of the semiconductor chip (in which the integrated circuit is implemented) is sent to a semiconductor manufacturing plant. Typically, the semiconductor chip is fabricated and then coupled to a package, whereas an electrical coupling is established between the padring of the semiconductor chip and the package.
During the physical layout design phase, the padring layout design is generated. The padring is an area where differing electrical, timing, physical, and logical views of the physical layout design come together. In particular, the padring is an interface for input signals, output signals, power signals, and ground signals between a semiconductor chip and off-chip components.
FIG. 1
illustrates a conventional padring layout design
10
. When combined with the trend of increasing in counts, fast clocks, and tight design schedules, the complexity of generating the padring layout design can be overwhelming. In order to satisfy this variety of constraints, a high level of control in partitioning, placement, and routing the various aspects of the padring layout design is required. This is often done by hand and can be a laborious process that does not lend itself to making changes in a repeatable manner.
Moreover, laying out a padring with a high pin count, fast clock, low skew, and/or tight design schedule is a daunting task that can occupy a designer for months. The sheer amount of details that must be tracked and incorporated into the padring layout design is a management task in and of itself. Figuring out a pinout that will route in the package and still satisfy the constraints on the die (or chip) involves knowledge in many areas. High clock rates and tight skew requirements demand precision and regularity in the layout of I/O cells and associated routes in the padring. Considerations dealing with the die such as the distance from the core of the die to the I/O area in the padring can disclose the fact that the distance is often too far to guarantee timing. On the package side, the layout of the bumps/bond pads in the padring has to be coordinated with the package to deliver a system that works together. Last minute changes and design schedule pressure can help this problem become a nightmare unless a systematic approach is used.
SUMMARY OF THE INVENTION
Methods for generating a padring layout design are described. In particular, these methods utilize automation while still allowing customization. The task of generating the padring layout design is greatly aided by software configured to generate padring layout designs.
The variety of problems encountered when laying out padrings are addressed. Automation is emphasized as much as possible so that more time can be used to solve the various problems that make each padring layout design unique. A framework in which regular patterns can be described, replicated, and tailored is provided. The padring is broken down into zones in which slots having bumps/bond pads areas, I/O cell areas, and/or edge logic cell areas are laid out in a regular pattern through an instantiation process. Edge logic, which is comprised of standard cells, is pulled from the core of the chip because these cells couple directly to I/O cells and are critical for timing. The framework allows the bumps/bond pads, I/O cells, and edge logic cells to be laid out in respective bumps/bond pads areas, I/O cell areas, and/or edge logic cell areas according to algorithms associated with the patterns and using a variety of maps which associate the logical netlist with the physical layout design.
In an embodiment, an editor and a GUI and a perl environment are provided which allow the resulting padring layout to be tailored to handle custom layout or exceptions in the patterns. This provides an environment for generating prototypes quickly to see if a pinout is feasible and determining packaging requirements. The padring layout design is generated in conjunction with package routing/selection and partitioning/floorplanning of the chip so that the chip-package-board system will work together. Finally, patterns can be saved and modified for use with future chips in the same chip family. This allows padring layout designs to be utilized despite shrinking and variability in future chip designs.
REFERENCES:
patent: 6194252 (2001-02-01), Yamaguchi
patent: 6523161 (2003-02-01), Gopalakrishnan et al.
patent: 6645841 (2003-11-01), Kever
Cao Phat X.
Reshape, Inc.
Wagner , Murabito & Hao LLP
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