Method of creating optimized tile-switch mapping...

Details Method of creating optimized tile-switch mapping... Method of creating optimized tile-switch mapping...

2005-10-12

2009-12-01

Ho, Duc C (Department: 2419)

Multiplex communications

Pathfinding or routing

Through a circuit switch

Reexamination Certificate

active

07626983

ABSTRACT:
Provided are a method of creating an optimized tile-switch mapping architecture in an on-chip bus, and a computer readable recording medium for recording the method. The method of creating a tile-switch mapping architecture includes first, second and third calculating steps. The method of creating a tile-switch mapping architecture minimizes the hop distance between cores when the mapping relationship between cores and tiles is determined, to thereby minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the method of creating a tile-switch mapping architecture presents a standard for comparing the optimization of other mapping architectures.

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patent: 7145903 (2006-12-01), Gutierrez
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patent: 2007/0239966 (2007-10-01), Georgiou et al.
patent: 03056567 (2003-07-01), None
English Abstract***.
Shashi Kumar, et al., “A Network on Chip Architecture and Design Methodolgy”Proceeding of the Society Annual Symposium on VLSI.

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