Stock material or miscellaneous articles – Composite – Of silicon containing
Reexamination Certificate
2002-01-23
2004-10-19
Stein, Stephen (Department: 1775)
Stock material or miscellaneous articles
Composite
Of silicon containing
C428S450000, C428S498000, C428S220000, C428S336000, C428S641000, C257S347000, C257S349000
Reexamination Certificate
active
06805962
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor substrate material, and more particularly to a method of fabricating thin, high-quality, substantially relaxed SiGe-on-insulator substrate materials. The relaxed SiGe-on-insulator substrate materials of the present invention can be used as a lattice mismatched template for creating a strained Si layer thereon by subsequent Si epitaxial overgrowth. Such strained Si layers have high carrier mobility and are useful in high-performance complementary metal oxide semiconductor (CMOS) applications. The present invention is also directed to SiGe-on-insulator substrate materials as well as structures which include at least the substrate materials.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high mobility structures for CMOS applications. Traditionally, the prior art method to implement this has been to grow strained Si layers on thick (on the order of from about 1 to about 5 micrometers) relaxed SiGe buffer layers.
Despite the high channel electron mobilities reported for prior art heterostructures; the use of thick SiGe buffer layers has several noticeable disadvantages associated therewith. First, thick SiGe buffer layers are not typically easy to integrate with existing Si-based CMOS technology. Second, the defect densities, including threading dislocations (TDs) and misfit dislocations, are from about 10
5
to about 10
8
defects/cm
2
which are still too high for realistic VSLI (very large scale integration) applications. Thirdly, the nature of the prior art structure precludes selective growth of the SiGe buffer layer so that circuits employing devices with strained Si, unstrained Si and SiGe materials are difficult, and in some instances, nearly impossible to integrate.
In order to produce relaxed SiGe material on a Si substrate, prior art methods typically grow a uniform, graded or stepped, SiGe layer to beyond the metastable critical thickness (i.e., the thickness beyond which dislocations form to relieve stress) and allow misfit dislocations to form, with the associated threading dislocations, through the SiGe buffer layer. Various buffer structures have been used to try to increase the length of the misfit dislocation section in the structures and thereby to decrease the TD density.
Another prior art approach, such as described in U.S. Pat. Nos. 5,461,243 and 5,759,898, both to Ek, et al., provides a structure with a strained and defect free semiconductor layer wherein a new strain relieve mechanism operates whereby the SiGe buffer layer relaxes without the generation of TDs within the SiGe layer.
Neither the conventional approaches, nor the alternative approaches described in the Ek, et al. patents provide a solution that substantially satisfies the material demands for device applications, i.e., sufficiently low TD density, substantially little or no misfit dislocation density and control over where the TD defects will be formed. As such, there is a continued need for developing a new and improved method of forming relaxed SiGe-on-insulator substrate materials which are thermodynamically stable against defect production.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating thin, high-quality, substantially relaxed SiGe-on-insulator substrate materials.
Another object of the present invention is to provide a method of fabricating thin, high-quality, substantially relaxed SiGe-on-insulator substrate materials which are thermodynamically stable against defect production such as misfit and threading dislocations.
A further object of the present invention is to provide a method of fabricating thin, high-quality, substantially relaxed SiGe-on-insulator substrate materials which are compatible with CMOS processing steps.
A yet further object of the present invention is to provide a method of fabricating thin, high-quality, substantially relaxed SiGe-on-insulator substrate materials which can then be used as lattice mismatched templates, i.e., substrates, for forming strained Si layers.
A still further object of the present invention is to provide strained Si/substantially relaxed SiGe-on-insulator structures which have high carrier mobility and are useful in high-performance CMOS applications.
These and other objects and advantages are achieved in the present invention by utilizing a method which includes first forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer, said first single crystal Si layer is present atop a barrier layer that is resistant to Ge diffusion; and thereafter a heating step is performed at a temperature which permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. It is noted that the substantially relaxed, single crystal layer is comprised of a homogeneous mixture of the SiGe or pure Ge layer as well as the first single crystal Si layer.
Following these steps of the present invention, a strained Si layer may be grown epitaxially atop the substantially relaxed single crystal SiGe layer to form a strained Si/relaxed SiGe-containing heterostructure that can be used in a variety of high-performance CMOS applications.
In some embodiments of the present invention, the first single crystal Si and barrier layer are components of a silicon-on-insulator (SOI) substrate. In other embodiments, the barrier layer is formed atop a surface of a semiconductor substrate, and thereafter the first single crystal Si layer is formed atop the barrier layer. The latter substrate material is a non-SOI substrate.
The present method also contemplates the use of barrier layers that are unpatterned (i.e., barrier layers that are continuous) or patterned (i.e., discrete and isolated barrier regions or islands which are surrounded by semiconductor material).
In yet another embodiment of the present invention, a Si cap layer is formed atop the SiGe or pure Ge layer prior to heating the structure. This embodiment of the present invention provides thermodynamically stable (in terms of preventing defect production) thin, substantially relaxed SiGe-on-insulator substrate materials. It is noted that the term “thin” when used in conjunction with the high-quality, substantially relaxed SiGe-on-insulator substrate material, denotes that the SiGe layer has a thickness of about 2000 nm or less, with a thickness of from about 10 to about 200 nm being more highly preferred.
Another aspect of the present invention relates to the SiGe-on-insulator substrate material that is formed utilizing the above-mentioned processing steps. Specifically, the inventive substrate material comprises a Si-containing substrate; an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate; and a substantially relaxed SiGe layer present atop the insulating region, wherein the substantially relaxed SiGe layer has a thickness of about 2000 nm or less.
A yet further aspect of the present invention relates to a heterostructure which includes at least the above-mentioned substrate material. Specifically, the heterostructure of the present invention comprises a Si-containing substrate; an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate;
a substantially relaxed SiGe layer present atop the insulating region, wherein the substantially relaxed SiGe layer has a thickness of about 2000 nm or less; and a strained Si layer formed atop the substantially relaxed SiGe layer.
Other aspects of the present invention relate to superlattice structures as well as templates for other lattice mismatched structures which include at least the SiGe-on-insulator substrate material of the present invention.
REFERENCES:
patent: 4866498 (1989-09-01), Myers
patent: 5461243 (1995-10-01), Ek et al.
patent: 5563428 (1996-10-01), Ek et al.
patent: 5667586 (1997-0
Bedell Stephen W.
Chu Jack O.
Fogel Keith E.
Koester Steven J.
Ott John Albrecht
International Business Machines - Corporation
Scully Scott Murphy & Presser
Stein Stephen
Trepp Robert M.
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