Method of correcting single errors

Details Method of correcting single errors Method of correcting single errors

1995-06-06

1997-05-20

Baker, Stephen M.

Excavating

371 376, H03M 1300

Patent

active

056319150

ABSTRACT:
Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit positions. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.

REFERENCES:
patent: 4319357 (1982-03-01), Bossen
patent: 4466099 (1984-08-01), Meltzer
patent: 4713816 (1987-12-01), Van Gils
patent: 4817095 (1989-03-01), Smelser et al.
patent: 4888773 (1989-12-01), Arlington et al.
patent: 4974147 (1990-11-01), Hanrahan et al.
patent: 4993028 (1991-02-01), Hillis
patent: 5027357 (1991-06-01), Yu et al.
patent: 5157669 (1992-10-01), Yu et al.
patent: 5172381 (1992-12-01), Karp et al.
patent: 5228046 (1993-07-01), Blake et al.
patent: 5241546 (1993-08-01), Peterson et al.
patent: 5299208 (1994-03-01), Blaum et al.
patent: 5313475 (1994-05-01), Cromer et al.
Chen, C., "Error Correcting Code for 3-Bit Package Error Detection", IBM Technical Disclosure Bulletin, vol. 22, No. 5, pp2004-2005. Oct. 1979.
"Roll-Mode Error Correction", IBM Technical Disclosure Bulletin, vol. 24, No. 1A, Jun. 1981, pp. 166-171.
"Consecutive Error Correction", IBM Technical Disclosure Bulletin, vol. 24, No. 11B, Apr. 1982, pp. 6048,6049.
"Error Checking for a Full Carry Look-ahead Adder", IBM Technical Disclosure Bulletin, vol. 27, No. 10B, Mar. 1985, pp. 6241-6248.
"Fully Self-contained Memory Card Extended Error Checking/Correcting Hardware Implementation", IBM Technical Disclosure Bulletin, vol. 31, No. 5, Oct. 1988, pp. 352-355.

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