Semiconductor device manufacturing: process – Gettering of substrate – By layers which are coated – contacted – or diffused
Reexamination Certificate
2000-07-19
2002-03-19
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Gettering of substrate
By layers which are coated, contacted, or diffused
C438S679000, C438S687000, C438S688000
Reexamination Certificate
active
06358821
ABSTRACT:
BACKGROUND OF THE INVENTION
A full-faced nitride film may be maintained on the backside of a wafer to prevent diffusion of copper species into the wafer during further processing.
U.S. Pat. No. 5,614,433 to Mandelman describes a method for forming an silicon-on-insulator (SOI) complimentary metal oxide semiconductor (CMOS) integrated circuit (IC), containing NFET's (N-type field effect transistors) and PFET's (P-type field effect transistors). An ion implantation (I/I) of aluminum (Al) is formed below the channel areas of NFET's that suppresses backside leakage in the PFET's and NFET's.
U.S. Pat. No. 5,296,385 to Moslehi et al. describes a method for semiconductor wafer backside preparation to prevent infrared light transmission through the wafer by either heavily damaging the wafer backside or heavily doping the back side wafer, and forming a top layer of silicon nitride over the wafer backside.
U.S. Pat. No. 5,360,765 to Kondo et al. describes a method for forming electrodes of a semiconductor device by forming a contact metal film over a silicon substrate after a cleaning process using a reverse sputtering of argon ions, and then forming a nickel film as a soldering metal on the contact metal film. The amount of argon atoms at the interface between the silicon substrate and the contact metal film is controlled to less than 4.0×10
14
atoms/cm
2
.
U.S. Pat. No. 5,964,953 to Mettifogo describes a process for removing aluminum contamination from the surface of an etched semiconductor wafer. The semiconductor wafer is first lapped in a lapping slurry containing aluminum, then etched, and then immersed in an aqueous bath comprising an alkaline component and a surfactant.
U.S. Pat. No. 5,958,796 to Prall et al. describes a method of cleaning waste matter from the backside of a semiconductor wafer substrate. A cover layer is deposited over the front side of the wafer and waste matter is removed from the backside of the wafer either by etching the waste matter from the backside with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization (CMP) process.
U.S. Pat. No. 3,997,368 to Petroff et al. describes a method of eliminating stacking faults in silicon devices by a gettering process. Before any high temperature processing steps, a stressed layer is formed on the backside of the wafer and is annealed to cause the nucleation sites to diffuse to a localized region near the back surface. The stressed layer may comprise silicon nitride or aluminum oxide. Enhanced gettering is achieved if interfacial misfit dislocations are introduced into the back surface by, for example, diffusion of phosphorus therein, before forming the stressed layer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to prevent transportation of copper on the back side of a wafer by a gettering process comprising sputtering a thin gettering layer on the wafer back side.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, (aluminum alloys, i.e.: aluminum-copper, aluminum-silicon, and aluminum-copper-silicon) is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.
REFERENCES:
patent: 3997368 (1976-12-01), Petroff et al.
patent: 5296385 (1994-03-01), Moslehi et al.
patent: 5360765 (1994-11-01), Kondo et al.
patent: 5614433 (1997-03-01), Mandelman
patent: 5757063 (1998-05-01), Tomita et al.
patent: 5958796 (1999-09-01), Prall et al.
patent: 5964953 (1999-10-01), Mettifogo
patent: 5994206 (1999-11-01), Gupta et al.
patent: 6043114 (2000-03-01), Kawagoe et al.
Kastl et al., “Gettering of Impurities from Semiconductor Materials”, IBM Technical Disclosure Bulletin, vol. 12, No. 11, p 1983 (1970).*
Morales-Acevedo et al., “Effect of High Temperature Annealing of Aluminum at the back of n+-p-p+siliconSolar Cells Upon Their Spectral and Electrical Characteristics”, Solid-State Electronics, 43, p 2075-2079 (1999).*
Santana et al., “Gettring effects by Aluminum Upon the Dark and Illuminated I-V Chacteristics of N+-P-P+ Silicon Solar Cell”, Solar Energy Materials & Solar Cells, vol. 62, p 369-378 (2000).*
Bunshah et al., Chapter 5 and 13, Noyes Publication (1982).
Aliyu Yakub
Chooi Simon
Gupta Subhash
Ho Paul Kwok Keung
Roy Sudipto Ranendra
Bowers Charles
Chartered Semiconductor Manufacturing Inc.
Pike Rosemary L. S.
Saile George O.
Smoot Stephen W.
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