Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2003-02-12
2004-09-28
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185290
Reexamination Certificate
active
06798696
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of controlling the operation (writing, erasing, and reading) of a semiconductor memory device configured by a plurality of non-volatile semiconductor memory chips.
2. Description of the Prior Art
In recent years, along with the wide spread of such portable devices as portable personal computers (PCs) and portable telephones, non-volatile semiconductor memories including flash memories are widely watched as information storage media employed for those portable devices.
Flash memories are roughly classified into two types according to the accessing unit length; NOR flash memory and AND/NAND flash memory. The NOR flash memory can be accessed in bytes at random, although it is small in capacity, a few megabytes at the most. The AND/NAND flash memory can be accessed in sectors while it has a capacity of a few tens of megabytes; each sector has a capacity of a few hundreds to a few thousands of bytes. The AND/NAND flash memory, which is a large capacity flash memory, is suitable as storages for which both low bit cost and sequential access performance are considered more important than random access performance in bytes. Card type semiconductor memory devices that employ the large capacity flash memories are now being manufactured by many corporations. A card type semiconductor memory device usually includes a plurality of flash memory chips to provide a larger capacity than that of the device itself.
FIG. 1
shows a system that employs such a semiconductor memory device. A host system
1
is, for example, a personal computer or digital camera. A semiconductor memory device
2
is connected to the host system
1
and writes/reads information according to the commands received from the host system
1
. The semiconductor memory device
2
is configured by a controller for controlling itself, an input/output interface
4
enabling commands and data to be sent/received between the host system
1
and the controller
3
, a buffer memory
5
, and a plurality of flash memory chips
6
for storing information. The controller
3
analyzes commands received from the host system
1
to control the flash memory chips
6
according to the analysis result and write/read information therein/therefrom. At this time, the controller
3
also erases information from each flash memory chip
6
as needed.
Next, a description will be made for the I/O interface
4
of the flash memory chips
6
. Unlike other memories, the large capacity flash memory chip
6
usually has no address terminal. The flash memory chip
6
accesses each sector to perform command input, address input, and data input/output through a common I/O terminal in a time sharing manner in accordance with a procedure predetermined for itself separately. Generally, the large capacity flash memory chip performs an input/output operation in units of eight bits. A 20 MHz I/O clock is used for most of the memories. The large capacity flash memory chip has a plurality of input terminals used for controlling the protocol. The High/Low levels of those input terminals can be combined in various ways to switch among such operations as command input, address input, and data input/output.
FIGS. 52 through 54
show how to access such a large capacity flash memory chip. To simplify the description, the protocol control signal will be omitted and only the access procedure concept will be described here. Hereinafter, the description will be made on the assumption that the I/O bus is eight bits in width, the I/O clock is 20 MHz, the command input cycle is one cycle, the sector address input cycle is two cycles, and the sector size is 2112 bytes.
At first, the writing procedure will be described with reference to FIG.
54
. Writing is done sequentially in the order of write command input CMD(W), write sector address input ADR, data input for one sector TR, write start command input CMD(SW), write end wait BUSY, and status read ST. When one sector data input ends, the inputted data is just stored in the buffer memory in the flash memory chip and not written in any memory cell therein yet. Writing in each memory cell in a specified sector starts at a write start command input. The flash memory chip disables simultaneous processing of two commands. When the next command is inputted just after the first one, the next write command is forced to wait for the completion of the preceding write command processing. And, after the flash memory is used for a certain time, the memory cells are degraded, thereby some sectors in the memory come to be disabled for correct writing. Consequently, the status of the flash memory chip is usually read after writing/erasing to/from each memory sector so as to check if the command processing is terminated normally therein. If the writing fails, the data is written in another sector (replacement processing). Each processing time in the above writing will become roughly as follows; the CMD(W) is 50 ns, the SDR is 100 ns, the TR is 110 &mgr;s, the CMD(WS) is 50 ns, the BUSY is 2 ms, and the ST is 50 ns.
Next, how to erase information from the large capacity flash memory chip will be described with reference to FIG.
55
. Erasing is performed sequentially in order of erase command input CMD(E), target sector address input ADR, erase start command input CMD(SE), wait for completion BUSY, and status read ST. Erasing from a memory cell in a specified sector starts at an erase start command input. Similarly to the writing described above, the next command input to the large capacity flash memory chip is forced to wait until the preceding erase command processing ends. And, similarly to the writing, the status of the large capacity flash memory chip is read usually after erasing of data from each memory sector to check if the command processing is terminated normally therein. When the erasing fails, the sector is registered as a defective one and replaced with another. Each processing time in the above erasing will become roughly as follows; the CMD(E) is 50 ns, the ADR is 100 ns, the CMD(ES) is 50 ns, the BUSY is 1 ms, and the ST is 50 ns.
Next, how to read information from the large capacity flash memory chip will be described with reference to FIG.
56
. Reading is performed sequentially in order of read command input CMD (R), target sector address input ADR, wait for reading to be prepared BUSY, and data read (output) TR. Reading (transferring) data from a memory cell in a specified sector provided in a chip to the buffer memory in the large capacity flash memory chip starts at a sector address input, concretely when the read data is transferred completely to the buffer memory provided in the large capacity flash memory chip. Each processing time in the above reading will become roughly as follows; the CMD(R) is 50 ns, the ADR is 100 ns, the TR is 110 &mgr;s, and the BUSY is 50 &mgr;s.
In a semiconductor memory device configured by some flash memory chips, data is divided into a plurality of data blocks and stored in a plurality of flash memory chips so as to improve the sequential access performance. In other words, processings are performed in a plurality of flash memory chips in parallel to improve the practical sequential access performance.
Hereinafter, a conventional writing method employed for a semiconductor memory device configured by four flash memory chips will be described with reference to some drawings.
FIG. 57
shows the conventional writing method described on the time axis in a case in which the data size is assumed as sector size ×4. Data D is divided into data blocks D
0
to D
3
, each having the same size as the sector size. The data blocks are written in different flash memory chips. In this case, the data block D
0
is written in the large capacity flash memory chip
0
, the data block D
1
is written in the large capacity flash memory chip
1
, the data block D
2
is written in the large capacity flash memory chip
2
, and the data block D
3
is written in the large capacity flash memory chip
3
respectively.
Kobayashi Naoki
Kurata Hideaki
Matsushita Toru
Miles & Stockbridge P.C.
Renesas Technology Corp.
Tran M.
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