Semiconductor device manufacturing: process – Including control responsive to sensed condition – Electrical characteristic sensed
Reexamination Certificate
2001-08-09
2003-06-24
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Electrical characteristic sensed
C118S665000
Reexamination Certificate
active
06582975
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of controlling the deposition of inter-level dielectric layers based upon electrical performance tests, and system for accomplishing same.
2. Description of the Related Art
There is a constant drive to reduce the size, or scale, of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of millions of transistors formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through a plurality of conductive interconnections, i.e., conductive lines and plugs.
Many modem integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive inter-connections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of alternating layers of conductive lines and conductive plugs formed in a plurality of inter-level dielectric layers formed on the device. The inter-level dielectric layer may be comprised of a variety of insulating materials, e.g., silicon dioxide, silicon oxynitride, etc. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.
By way of background, an illustrative transistor
10
that may be included in such an integrated circuit device is shown in FIG.
1
. The transistor
10
is generally comprised of a gate insulation layer
14
, a gate electrode
16
, sidewall spacers
20
and a plurality of source/drain regions
18
formed in an active area
15
of a semiconducting wafer
12
between isolation regions
25
. The gate insulation layer
14
may be formed from a variety of materials, such as silicon dioxide. The gate electrode
16
may also be formed from a variety of materials, such as polysilicon. The source and drain regions
18
may be formed by performing one or more ion implantation processes during which a dopant material is implanted into the wafer
12
.
In one illustrative process flow, a first inter-level dielectric layer
26
is formed above the transistor
10
, and a plurality of openings
24
are formed in the first inter-level dielectric layer
26
. Thereafter, the openings
24
are filled with a conductive material, such as a metal, to form conductive plugs
22
. In the illustrative transistor
10
shown in
FIG. 1
, the conductive plugs
22
are electrically coupled to the source and drain regions
18
of the transistor
10
. Within the semiconductor industry, the conductive plugs
22
may be referred to as either contacts or vias. In general, conductive plugs that are coupled to regions of a transistor, e.g., source/drain regions, are referred to as contacts. Conductive plugs that serve other functions, such as connecting two different layers of conductive lines, are known as vias. However, different terminology may be employed within the industry to distinguish conductive plugs on this basis. Thus, as used herein, the term conductive plugs should be understood to include both contacts and vias.
Thereafter, a second inter-level dielectric layer
32
may be formed above the first inter-level dielectric layer
26
. Multiple openings
30
may be formed in the second inter-level dielectric layer
32
, and the openings
30
may thereafter be filled with a conductive material to form conductive lines
28
. Although only a single level of conductive plugs and a single level of conductive lines are depicted in
FIG. 1
, there may be multiple levels of plugs and lines interleaved with one another. This interconnected network of plugs and lines allows electrical signals to propagate throughout the integrated circuit device. The techniques used for forming the various components depicted in
FIG. 1
are known to those skilled in the art and will not be repeated here in any detail.
The conductive plugs
22
and conductive lines
28
may be of any size or configuration, they may be formed by any of a variety of techniques, and they may be comprised of any of a variety of conductive materials. For example, the conductive plugs
22
depicted in
FIG. 1
may have a circular cross-section, i.e., the plug may be essentially a cylinder of material. However, the plug
22
can be made into any of a variety of shapes, e.g., square, rectangular, etc. Further, the inter-level dielectric layers
26
,
32
may be comprised of any insulating material, such as silicon dioxide or a low-k dielectric, and there may be many such inter-level dielectric layers on a completed integrated circuit device. Typically, the inter-level dielectric layer
26
is formed by depositing the layer
26
, and thereafter, subjecting it to a planarization operation, such as a chemical mechanical polishing (“CMP”) operation, so as to produce an essentially planar surface
27
. Next, the plurality of openings
24
are formed in the inter-level dielectric layer
26
by performing known photolithography and etching processes, e.g., an anisotropic plasma etching process.
Thereafter, a layer (not shown) of the appropriate conductive material, e.g., a metal, may be blanket-deposited, or otherwise formed, over the transistor
10
, thereby filling the openings
24
formed in the first inter-level dielectric layer
26
. The metal layer (not shown) may thereafter be subjected to a CMP process to remove the excess material, thereby leaving the conductive plugs
22
in the openings
24
. A barrier metal layer (not shown) may be formed in the opening prior to the metal deposition process but such details are omitted for purposes of clarity.
Next, the inter-level dielectric layer
32
is formed above the inter-level dielectric layer
26
, and the plurality of openings
30
may be defined in the inter-level dielectric layer
32
through use of traditional photolithography and etching processes. Thereafter, the conductive line
28
is formed in the opening
30
in the inter-level dielectric layer
32
. As with the plug
22
, the conductive line
28
may be formed in any of a variety of shapes, using any of a variety of known techniques for forming such lines, and may be comprised of a variety of materials. For example, the conductive line
28
may be comprised of tungsten, aluminum etc. That is, the conductive lines
28
may be formed by depositing a layer of the appropriate conductive material in the openings
30
, and, thereafter, performing a chemical mechanical polishing process.
As stated previously, there is a constant drive to increase the operating speed of integrated circuit devices. However, one factor that may tend to decrease the operating speed of the completed device is the capacitive coupling between the various conductive interconnection, i.e., lines and plugs, of the device when it is operational. This capacitive coupling is undesirable in that it must be charged and discharged on every operational cycle, thereby reducing the switching speed of the transistor. Moreover, such capacitive coupling tends to increase the power consumption of the completed device.
In general, the capacitive coupling of adjacent structures, e.g., lines and plugs, is inversely proportional to the distance (“d”) between the structures and directly proportional to the dielectric constant (“k”) of the material positioned between the structures. Unfortunately, as the packing densities of modern integrated circuit devices continues to increase, the spacing, both horizontal and vertical, between condu
Advanced Micro Devices , Inc.
Pert Evan
Williams Morgan & Amerson P.C.
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