Method of controlling the chemical mechanical polishing of...

Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed

Reexamination Certificate

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C438S005000, C438S014000, C438S692000, C216S084000, C216S088000, C216S089000

Reexamination Certificate

active

06936480

ABSTRACT:
An improved CMP controller allows the calculation of the polish time required for removing a patterned layer stack to a desired final thickness, wherein the initial layer thickness of each layer contained in the layer stack is employed. Moreover, a topography factor characterizing the surface structure of the layer stack and a selectivity characterizing the ratio of removal rates between adjacent material layers are used. Furthermore, a state variable of the controller represented by the removal rate of one of the layers may periodically be updated on the basis of the previously calculated polish time and a measurement value of the finally obtained layer thickness. The improved controller is particularly advantageous in the CMP process for STI isolation structures, in which the final thickness of a CMP stop layer, having a significantly reduced removal rate compared to the overlying dielectric layer, has to be precisely controlled.

REFERENCES:
patent: 6171174 (2001-01-01), Campbell et al.
patent: 6230069 (2001-05-01), Campbell et al.
patent: 6517412 (2003-02-01), Lee et al.
patent: 2002/0058460 (2002-05-01), Lee et al.
patent: 1 092 505 (2001-04-01), None
patent: 10106984 (1998-04-01), None
patent: WO 98/14306 (1998-04-01), None

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