Method of controlling stress in a film

Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from solid or gel state

Reexamination Certificate

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Reexamination Certificate

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06328794

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of controlling the stress in thin films of the type used in semiconductor fabrication, and, more particularly, to a method of controlling the state and amount of stress in material used to fill high aspect ratio trenches in silicon substrates.
BACKGROUND OF THE INVENTION
In trench storage dynamic random access memory (DRAM) devices, the capacitive elements of the devices are typically formed in deep trenches provided in the silicon substrate. As used herein, “deep” or “high aspect ratio” trenches are trenches having a depth that is typically
10
or more times the diameter of the trench. Although these DRAM devices function highly satisfactorily, as a result of the continuing effort to increase DRAM density and performance, a need exists to increase the period of time such devices retain a charge.
Retention time is adversely affected by charge leakage occurring via interstitial dislocations in portions of the silicon substrate adjacent the trench in which the capacitor is formed. Such dislocations are apparently caused, in part, by inherent compressive stresses in the trench fill material used in the fabrication of the capacitive device. The compressive stress in the fill causes the walls of the trench to bow outwardly, which deflection of the trench walls is believed to introduce dislocations in the substrate adjacent the walls of the trench.
Very high temperature anneal processes have been used to reduce the stress in oxide films. Unfortunately, such processes do not appear to have any appreciable affect on the stress in films of polycrystalline silicon (“poly-Si”). No other process are believed to be known for providing significant reduction in the stress in poly-Si films, particularly when used as the fill material for trench storage DRAMs.
Under certain conditions, voids will form in the fill of deep-trench capacitors during the formation thereof. One technique for minimizing the formation of such voids is disclosed in U.S. Pat. No. 4,977,104 to Sawada et al. This technique involves (a) depositing a first doped semiconductor film on a semiconductor substrate, (b) depositing a second undoped semiconductor film on the doped film, and (c) heat treating the substrate to cause the dopants to diffuse from the first film to the second film. In one example discussed in the Sawada et al. patent, a trench electrode having a phosphorous dopant concentration of 1×10
20
/cm
3
is formed using the method disclosed in this patent.
In the field of micro-mechanical devices, the need exists under certain circumstances to deform a given structure so that it assumes a predetermined configuration. For instance, silicon micro-mechanical cantilever structures of the type used in light deflector arrays and pressure sensors are known to bend in an undesirable manner due to intrinsic or thermal stresses in such structures. Under certain circumstances, such structures would have greater functionality and/or utility if such deformation could be controlled or eliminated.
SUMMARY OF THE INVENTION
The present invention is a method of depositing a film of material on a substrate so that the film has a predetermined state and amount of stress. By controlling the stress in the film, the forces applied by the layer to adjacent regions of the substrate may be precisely controlled.
In one embodiment of the invention, the method involves depositing a layer of crystalline material on a surface of a substrate. Then, a layer of amorphous crystallizable material is deposited on the crystalline layer. Finally, the substrate is heated at a temperature and for a time sufficient to cause the amorphous layer to at least partially crystallize. The layer of amorphous material contracts upon crystallization, thereby reducing the compressive stress in the layer, or, in some cases, changing its state to a tensile stress. Such reduction in, or change in state of, stress in the formerly amorphous layer in turn modifies the forces applied to is the structure by the crystalline layer and formerly amorphous layer. Because the state and level of stress in the layer varies primarily as a function of the thickness of the layer, the stress in the layer may be precisely controlled by controlling the thickness of the layer. By controlling the state and level of stress in the formerly amorphous layer in this manner, the forces applied to the substrate by the composite layer consisting of the crystalline layer and formerly amorphous layer may be accurately controlled.
In another embodiment of the invention, he method involves depositing a layer of compressively stressed amorphous material on a selected portion of a substrate. Then, the substrate is heated at a temperature and pressure and for a period of time sufficient to cause the layer of amorphous material to at least partially crystallize. By controlling the thickness of the layer of amorphous material, the forces such layer applies to the substrate may be carefully controlled.
In yet another embodiment of the invention, a layer of relatively lightly doped polycrystalline silicon is deposited on the walls of a deep trench formed in a substrate. Then, a layer of intrinsic amorphous silicon is deposited on the layer of polycrystalline silicon to a thickness sufficient to fill the entire trench with silicon. Finally, the substrate is heated to cause the amorphous layer to crystallize and to cause the dopant in the layer of polycrystalline material to diffuse into the layer of formerly amorphous silicon. The dopant level in the polycrystalline silicon layer is selected so that after the heating step is completed, the level of dopant in this layer and in the formerly amorphous layer is lower than dopant levels that can be readily and repeatedly obtained by conventional deposition techniques. Such relatively light doping of the polycrystalline silicon and formerly amorphous silicon layers is believed to reduce the stress in such layers to a level below that ordinarily achieved in silicon trench fill doped to higher, more conventional levels. Thus, the combination of causing the amorphous layer to crystallize and reducing the overall dopant levels in the layers provides a very effective method of reducing stress in trench fill.


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Wolf et al., Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, USA, pp. 114-117, 124, 140, 152-154, 175-183, 198-200, 228, 1986.*
Wolf et al, Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, USA, Ch. 4, pp. 109-123, 1986.*
Wolf, Silicon Processing for the VLSi Era, vol. 2: Process Integration, Lattice Press, Sunset Beach, CA, USA, pp. 51-58, 600-609, 1990, 1986.

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