Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-02-05
2001-11-20
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S189011
Reexamination Certificate
active
06320786
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89127627, filed Dec. 22, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of using an NROM. More particularly, the present invention relates to a method of controlling a multi-state NROM.
2. Description of Related Art
FIG. 1
is a schematic cross-sectional view of a conventional flash memory cell. As shown in
FIG. 1
, the flash memory cell includes a gate electrode that consists of a floating gate
12
and a control gate
14
. The floating gate
12
is a polysilicon layer for holding electric charges. The floating gate
12
is always in a ‘floating’ state because the gate
12
is disconnected from external circuits. The control gate
14
is used for controlling data access. Each memory cell is capable of holding a single bit. In other words, each memory cell can only distinguish between logic states ‘0’ and ‘1’.
FIG. 2
is a simple graph showing the conventional method of distinguishing between logic ‘1’ and ‘0’ in a memory cell. As shown in
FIG. 2
, a voltage Vread is applied to the gate when data access is required. If the threshold voltage of the memory cell is smaller than Vread (for example, Vt
1
), a large current is sensed implying a logic state ‘1’. On the other hand, if the threshold voltage of the memory cell is greater than Vread (for example, Vt
2
), very small current is detected implying a logic state ‘0’.
Following the introduction of high-density flash memory, memory capable of distinguishing a multiple of state is developed.
FIG. 3
is a graph showing a conventional method of distinguishing four different states in a memory cell (including ‘00’, ‘01’, ‘10’ and ‘11’). As shown in
FIG. 3
, three standard reading voltages Vr
1
, Vr
2
and Vr
3
are set to distinguish between four different types of threshold voltages (Vt
1
, Vt
2
, Vt
3
and Vt
4
). However, threshold voltage region cannot be made very large because Fowler-Nordeim (F-N) tunneling current is easily affected by any deviation in the processing parameters such as the variation of tunneling oxide thickness and the variation of tunneling junction area. The deviation of such F-N tunneling current often affects the size of threshold voltage region for accessing data inside a memory cell array. Together with dimensional limitations of a chip, most flash memory cell can only support two storage states. Hence, a higher memory storage capacity is difficult to attain.
On the other hand, an NROM memory cell is able to hold a data bit in the drain terminal and the source terminal. However, the drain terminal and the source terminal need to be connected in reverse during programming and reading, leading to the need for quite complicated control circuits. Moreover, if a neighboring bit undergoes some programming when current is being measured, the so-called second-bit effect may occur leading to a considerable reduction of the original high current. In addition, since both terminals are employed to hold data, scaling down is made more difficult.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of controlling a multi-state NROM that utilizes a non-symmetrical charge trapping characteristic and different drain voltages V
D
to distinguish between differently programmed threshold voltage Vt. Thus, the NROM memory cell has a larger operating capacity for multi-state storage.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of controlling a multi-state NROM. The NROM comprises of a substrate, a source terminal and a drain terminal in the substrate and a gate electrode. The gate electrode is located above the substrate between the source terminal and the drain terminal. The gate electrode is a multi-layered stack that includes, from bottom to top, a first oxide layer, a nitride layer, a second oxide layer and a polysilicon layer. The nitride layer can trap electric charges and hence can serve as a charge holder.
The method of controlling the multi-state NROM includes the following steps. First, a programming step is executed to inject electric charges into the nitride layer so that electric charges are trapped. The amount of electric charges trapped inside the nitride layer is precisely controlled so that the memory cell can have different threshold voltages. To read from the memory cell, a first variable voltage is applied to the gate electrode. According to the range of a second variable voltage applied to the drain terminal, three different potential levels, from the smallest to the largest, including a first potential level, a second potential level and a third potential level are set. The second input voltage is adjusted to the first potential level. When a high current is sensed, a first storage state is assumed. If little current is detected, the second input voltage is adjusted to the second potential level. When a high current is sensed, a second storage state is assumed. On the other hand, if little current is detected, the second input voltage is adjusted to the third potential level. Similarly, if a high current is sensed, a third storage state is assumed. Conversely, when little current is detected, a fourth storage state is assumed.
The difference between the first potential level and the second potential level and the difference between the second potential level and the third potential level can be identically set, for example, at 0.5V, 1.25V and 2V respectively. The first variable voltage can be set to a fixed voltage. On the other hand, if the first variable voltage is variable, the range of various read voltage regions (a total of three) of the drain terminal can be increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6154390 (2000-11-01), Yang
patent: 6191677 (2001-02-01), Lee
patent: 6259627 (2001-07-01), Wong
Chang Yao Wen
Lu Tao Cheng
Tsai Wen Jer
Huang Jiawei
J.C. Patents
Le Vu A.
Macronix International Co. Ltd.
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