Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-03-30
2003-04-01
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S189011, C365S189050
Reexamination Certificate
active
06542429
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of controlling a line memory, and particularly to a method of controlling an image data writing/reading operation of a line memory for use in a signal processing system for carrying out image compression processing such as JPEG or the like.
2. Description of the Related Art
When still image compression processing, for example, JPEG image compression processing is carried out, image data of 8×8 pixels in horizontal and vertical directions are required. In a case where this JPEG image compression processing is applied to a signal processing system of a camera system using, for example, a CCD image pickup element as an image pickup device, for image data of 8×8 pixels or more, image data must be temporarily written into a line memory and then successively read out on a 8×8-line basis every data in the horizontal direction because the image data obtained by subjecting the signal processing to image pickup signals of the CCD image pickup element are output line by line.
FIG. 15
shows the construction of a signal processing system of a conventional camera system using a CCD image pickup element as an image pickup device.
In
FIG. 15
, the output signal (image pickup signal) of a CCD image pickup element
101
is subjected to various signal processing in a signal processing circuit
102
and then input to a line memory
103
.
FIG. 16
shows an image for the original image of image data output from the signal processing circuit
102
. In
FIG. 16
, an arrow (
1
) represents the order of the image data output from the signal processing circuit
102
. The area indicated by an arrow (
2
) represents a block (8 pixels in horizontal direction and 8 pixels in vertical direction) which is the processing unit of the JPEG image compression.
As an example, the image size is set to 128 pixels in the horizontal direction×64 pixels in the vertical direction. When the JPEG image compression processing is carried out on the image data having this image size, a line memory having a memory capacity of 128 pixels in the horizontal direction, 8 pixels (8 lines) in the vertical direction and 8 bits for each data is used as the line memory
103
. At this time, the addresses are set to 1 to 1024. Further, this memory capacity is defined as one bank.
The control of the data write/read operation to the line memory
103
having a capacity of one bank is carried out by a line memory controller
104
. The data read out from the line memory
103
are supplied to a DCT (Discrete Cosine Transformation) circuit
105
of a JPEG module.
FIG. 17A
shows the writing order of data into the line memory
103
and
FIG. 17B
shows the reading order of data from the line memory
103
. That is, as is apparent from
FIG. 17A
, in the data writing operation, 128 pixels (data) are set on one line and the image data are successively written into the line memory
103
line by line from a first line till an eighth line. On the other hand, as is apparent from
FIG. 17B
, in the data reading operation, 8 pixels in one line×8 lines are set as one block and the image data are successively read out data by data every line within each block.
In the case of the prior art
1
using the line memory
103
having a memory capacity of only one bank as described above, the image data are successively written into the line memory
103
line by line whereas the image data are successively read out data by data every line on a block basis. Therefore, as shown in the timing chart of
FIG. 18
, “wait” is applied to the data reading processing every time the reading operation of the data on one line in the horizontal direction of 8×8 pixels is finished.
Further, since the memory capacity of the line memory
103
is one bank, the data reading operation and the data writing operation must be alternately carried out. Therefore, the data from the signal processing circuit
102
cannot be processed on a real-time basis. That is, the data reading operation and the data writing operation can be alternately carried out at the first stage of the first line, however, the image data cannot be processed on a real-time basis because only one data can be stored in one address.
On the other hand, a signal processing system using a line memory having a memory capacity of 2 banks is also known. As shown in
FIG. 19
, the signal processing system of the prior art
2
has two line memories
103
A and
103
B each having a memory capacity of one bank, and image data of 128 pixels×8 pixels in image size are alternately written into each of the line memories
103
A and
103
B while the image data are alternately read out from each of the line memories
103
A and
103
B which does not carry out the writing operation, and then supplied to a DCT circuit
105
of the JPEG module through a selection switch
106
.
In the case of the prior art
2
, as is apparent from the timing chart of
FIG. 20
, it is possible to carry out the writing/reading operation of the image data to the line memory on a real-time basis. However, the memory capacity is twice as large as that of the prior art
1
because it has a memory capacity corresponding to two banks. Therefore, the circuit scale of the prior art
2
is large and thus the cost is increased.
SUMMARY OF THE INVENTION
The present invention has been implemented in view of the foregoing situation, and has an object to provide a line memory controlling method which can perform the real-time processing of image data with a smaller amount of memory capacity.
According to the present invention, there is provided a line memory control method for temporarily writing input image data into a line memory and reading out the image data written in the line memory on a block basis, comprising: a pre-processing step of reducing the data rate of the input image data; a writing step of successively writing the pre-processed image data into a line memory every line by using a first address; and a reading/writing step of reading out the image data on a line basis every block by using a second address different from the first address after said writing step is finished, and writing image data into a read-out block by using the second address.
When the image data are written into the line memory, the data rate of the input image data is first reduced in the pre-processing. Therefore, even when the line memory is a single port, the writing and reading operations of the image data to the line memory can be carried out in parallel. After the image data of the image size which have been subjected to the pre-processing are successively written into the line memory line by line, the processing is shifted to the reading operation of the image data on a block basis. At this time, image data are successively read out on a line basis every block, and image data are successively written at the same addresses as used in the reading operation into a block from which the image data have been read out. The reading/writing processing is carried out on all the blocks.
REFERENCES:
patent: 6026194 (2002-02-01), Torikai et al.
patent: 6388706 (2002-05-01), Takizawa et al.
Koyanagi Daisuke
Ueki Yuichi
Frommer William S.
Frommer & Lawrence & Haug LLP
Le Vu A.
Sony Corporation
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