Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2000-01-05
2002-03-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C438S007000, C438S017000, C438S018000
Reexamination Certificate
active
06352867
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to the field of semiconductor processing, and, more particularly, to a method of controlling feature dimensions during etching processes.
2. Description of the Related Art
There is a constant drive to reduce the size, or scale, of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of transistors formed above the surface of a semiconducting substrate.
By way of background, an illustrative NMOS transistor
10
that may be included in such an integrated circuit device is shown in FIG.
1
. The transistor
10
is generally comprised of a gate dielectric
14
, a gate conductor
16
, and a plurality of source/drain regions
18
formed in a semiconducting substrate
12
. The gate dielectric
14
may be formed from a variety of dielectric materials, such as silicon dioxide. The gate conductor
16
may also be formed from a variety of materials, such as polysilicon. The source and drain regions
18
may be formed by one or more ion implantation processes in which a dopant material is implanted into the substrate
12
.
Next, a first dielectric layer
26
is formed above the transistor
10
, and a plurality of vias or openings
24
are formed in the first dielectric layer
26
. Thereafter, the vias
24
are filled with a conductive material, such as a metal, to form contacts
22
. In the illustrative transistor
10
shown in
FIG. 1
, the contacts
22
are electrically coupled to the source and drain regions
18
of the transistor
10
. Thereafter, a second dielectric layer
32
may be formed above the first dielectric layer
26
. Multiple openings
30
may be formed in the second dielectric layer
32
, and the openings
30
may thereafter be filled with a conductive material to form conductive lines
28
. Although only a single level of contacts and a single level of conductive lines are depicted in
FIG. 1
, there may be multiple levels of contacts and lines interleaved with one another. This interconnected network of contacts and lines allows electrical signals to propagate throughout the integrated circuit device. The techniques used for forming the various components depicted in
FIG. 1
are known to those skilled in the art and will not be repeated here in any detail.
As feature sizes have decreased, the maintenance and control of the dimensions of the various components or features of a transistor, e.g, the channel length “L” which roughly corresponds to the width “W” of the gate electrode
16
, has become very important. For example, small changes in the channel length of a transistor may negatively impact transistor performance. All other things being equal, the greater the channel length, the slower the transistor will operate, and vice versa. Therefore, great care is taken during manufacturing operations to define the various features of a transistor, e.g., gate width, very precisely.
However, processing operations performed after such features have been defined may negatively impact the ability to maintain or control these precisely formed features. After various features of a transistor are formed, the partially formed transistor may be subjected to one or more wet etching processes in a chemical bath during which an entire wafer, or lot of wafers, is submerged in a bath comprised of many chemical components for a set period of time. These etching processes may be performed for a variety of reasons. For example, a partially formed transistor may be subjected to a wet etching process to generally clean the surface of the wafer or to remove layers of material that are no longer desired, e.g., antireflective coatings.
In some situations, the partially formed transistor with the features defined on the transistor is subjected to subsequent etching processes that may also attack the materials out of which the features are defined. Moreover, the etching rate of these chemical baths is dependent upon, among other things, the concentration of the various chemicals of the bath. Such concentrations may vary over time for a variety of reasons. For example, these types of chemical baths may be replenished on a periodic or intermittent basis which inherently leads to variations in the concentration of the various chemical components. Additionally, some chemicals used in such baths tend to evaporate relatively quickly, or break down into water plus some other residual components. These variations in etch chemistry, regardless of their source, create variations in the etching rate of the chemical bath.
The variation in etching rates of the bath can be problematic in a number of respects. For example, in the case where a feature size, e.g., a gate width, is actually manufactured to the lowest end of a tolerance range, performing an etching process using a bath having an etch chemistry that produces the fastest allowable etch rate for a standard duration may further reduce the feature size beyond acceptable limits. Additionally, maintaining control of defined feature sizes is difficult since the etch rate of such subsequent chemical baths may be varied.
The present invention is directed to a method of manufacturing semiconductor device that minimizes or reduces some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method of manufacturing semiconductor devices. In one illustrative embodiment, the method comprises determining an etch rate for a chemical bath in which the device will be placed, and determining a manufactured size of a feature formed above a semiconducting substrate. The method further comprises determining a duration of an etch process to be performed in the bath and to which the feature will be exposed based upon the etch rate of the bath and the manufactured size of the feature. Thereafter, the etch process is performed in the bath for the determined duration.
In another illustrative embodiment, the method comprises determining an etch rate for a chemical bath, and determining the size of a gate electrode or a variation in the size of a gate electrode as compared to its design size. The method further comprises determining a duration of an etch process to be performed in the bath and to which the gate electrode will be exposed based upon the determined etch rate and the size, or variation in size, of the gate electrode. Thereafter, the etch process is performed in the bath for the determined duration.
REFERENCES:
patent: 4957590 (1990-09-01), Douglas
Wolf S., Tauber R. “Silicon Processing for the VLSI Era, vol. 1:Process Technology”, Lattice Press, California, 1986, pp. 514-537.
Campbell William Jarrett
Couteau Terri A.
Toprac Anthony J.
Rocchegiani Renzo N.
Williams Morgan & Amerson P.C.
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